Searched refs:CLK_DIV_CDREX_VAL (Results 1 – 2 of 2) sorted by relevance
521 #define CLK_DIV_CDREX_VAL ((MCLK_DPHY_RATIO << 24) \ macro777 #define CLK_DIV_CDREX_VAL 0x17010100 macro
728 writel(CLK_DIV_CDREX_VAL, &clk->div_cdrex); in exynos5250_system_clock_init()