Searched refs:CLK_DIV_CPU0_VAL (Results 1 – 6 of 6) sorted by relevance
62 writel(CLK_DIV_CPU0_VAL, &clk->div_cpu0); in system_clock_init()
510 #define CLK_DIV_CPU0_VAL NOT_AVAILABLE macro780 #define CLK_DIV_CPU0_VAL 0x01440020 macro
52 #define CLK_DIV_CPU0_VAL ((APLL_RATIO << 24) \ macro
813 writel(CLK_DIV_CPU0_VAL, &clk->div_cpu0); in exynos5420_system_clock_init()
322 writel(CLK_DIV_CPU0_VAL, (unsigned int)&clk->div_cpu0); in board_clock_init()
37 #define CLK_DIV_CPU0_VAL ((APLL_RATIO << 24) \ macro