Searched refs:CLK_DIV_FSYS2_VAL (Results 1 – 6 of 6) sorted by relevance
70 writel(CLK_DIV_FSYS2_VAL, &clk->div_fsys2); in system_clock_init()
490 #define CLK_DIV_FSYS2_VAL NOT_AVAILABLE macro758 #define CLK_DIV_FSYS2_VAL 0x041d0000 macro
214 #define CLK_DIV_FSYS2_VAL ((MMC3_PRE_RATIO << 24) \ macro
943 writel(CLK_DIV_FSYS2_VAL, &clk->div_fsys2); in exynos5420_system_clock_init()
330 writel(CLK_DIV_FSYS2_VAL, (unsigned int)&clk->div_fsys2); in board_clock_init()
166 #define CLK_DIV_FSYS2_VAL ((MMC3_PRE_RATIO << 24) \ macro