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Searched refs:CLK_DIV_FSYS3_VAL (Results 1 – 4 of 4) sorted by relevance

/external/u-boot/arch/arm/mach-exynos/
Dclock_init_exynos4.c71 writel(CLK_DIV_FSYS3_VAL, &clk->div_fsys3); in system_clock_init()
Dexynos4_setup.h222 #define CLK_DIV_FSYS3_VAL ((MMC4_PRE_RATIO << 8) \ macro
/external/u-boot/board/samsung/trats/
Dtrats.c331 writel(CLK_DIV_FSYS3_VAL, (unsigned int)&clk->div_fsys3); in board_clock_init()
Dsetup.h174 #define CLK_DIV_FSYS3_VAL ((MMC4_PRE_RATIO << 8) \ macro