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Searched refs:CMP1 (Results 1 – 25 of 53) sorted by relevance

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/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/InstCombine/
Dcompare-udiv.ll6 ; CHECK-NEXT: [[CMP1:%.*]] = icmp ugt i32 %d, %n
7 ; CHECK-NEXT: ret i1 [[CMP1]]
16 ; CHECK-NEXT: [[CMP1:%.*]] = icmp ugt <2 x i32> %d, %n
17 ; CHECK-NEXT: ret <2 x i1> [[CMP1]]
26 ; CHECK-NEXT: [[CMP1:%.*]] = icmp ugt i32 %d, 64
27 ; CHECK-NEXT: ret i1 [[CMP1]]
36 ; CHECK-NEXT: [[CMP1:%.*]] = icmp ugt <2 x i32> %d, <i32 64, i32 63>
37 ; CHECK-NEXT: ret <2 x i1> [[CMP1]]
46 ; CHECK-NEXT: [[CMP1:%.*]] = icmp ule i32 %d, %n
47 ; CHECK-NEXT: ret i1 [[CMP1]]
[all …]
Dclamp-to-minmax.ll204 ; CHECK-NEXT: [[CMP1:%.*]] = fcmp ole float [[X]], 0.000000e+00
205 ; CHECK-NEXT: [[R:%.*]] = select i1 [[CMP1]], float 0.000000e+00, float [[MIN]]
219 ; CHECK-NEXT: [[CMP1:%.*]] = fcmp olt float [[X]], 0.000000e+00
220 ; CHECK-NEXT: [[R:%.*]] = select i1 [[CMP1]], float 0.000000e+00, float [[MIN]]
242 ; CHECK-NEXT: [[CMP1:%.*]] = fcmp olt float [[X]], 1.000000e+00
243 ; CHECK-NEXT: [[R:%.*]] = select i1 [[CMP1]], float 1.000000e+00, float [[MIN]]
258 ; CHECK-NEXT: [[CMP1:%.*]] = fcmp olt float [[X]], 1.000000e+00
259 ; CHECK-NEXT: [[R:%.*]] = select i1 [[CMP1]], float 1.000000e+00, float [[MIN]]
275 ; CHECK-NEXT: [[CMP1:%.*]] = fcmp ole float [[X]], 1.000000e+00
276 ; CHECK-NEXT: [[R:%.*]] = select i1 [[CMP1]], float 1.000000e+00, float [[MIN]]
[all …]
Dsmax-icmp.ll140 ; CHECK-NEXT: [[CMP1:%.*]] = icmp sgt i32 %y, %x
141 ; CHECK-NEXT: ret i1 [[CMP1]]
169 ; CHECK-NEXT: [[CMP1:%.*]] = icmp slt i32 [[X]], %y
170 ; CHECK-NEXT: ret i1 [[CMP1]]
196 ; CHECK-NEXT: [[CMP1:%.*]] = icmp sgt i32 %y, %x
197 ; CHECK-NEXT: ret i1 [[CMP1]]
225 ; CHECK-NEXT: [[CMP1:%.*]] = icmp slt i32 [[X]], %y
226 ; CHECK-NEXT: ret i1 [[CMP1]]
Dumin-icmp.ll140 ; CHECK-NEXT: [[CMP1:%.*]] = icmp ult i32 %y, %x
141 ; CHECK-NEXT: ret i1 [[CMP1]]
169 ; CHECK-NEXT: [[CMP1:%.*]] = icmp ugt i32 [[X]], %y
170 ; CHECK-NEXT: ret i1 [[CMP1]]
196 ; CHECK-NEXT: [[CMP1:%.*]] = icmp ult i32 %y, %x
197 ; CHECK-NEXT: ret i1 [[CMP1]]
225 ; CHECK-NEXT: [[CMP1:%.*]] = icmp ugt i32 [[X]], %y
226 ; CHECK-NEXT: ret i1 [[CMP1]]
Dumax-icmp.ll140 ; CHECK-NEXT: [[CMP1:%.*]] = icmp ugt i32 %y, %x
141 ; CHECK-NEXT: ret i1 [[CMP1]]
169 ; CHECK-NEXT: [[CMP1:%.*]] = icmp ult i32 [[X]], %y
170 ; CHECK-NEXT: ret i1 [[CMP1]]
196 ; CHECK-NEXT: [[CMP1:%.*]] = icmp ugt i32 %y, %x
197 ; CHECK-NEXT: ret i1 [[CMP1]]
225 ; CHECK-NEXT: [[CMP1:%.*]] = icmp ult i32 [[X]], %y
226 ; CHECK-NEXT: ret i1 [[CMP1]]
Dand-fcmp.ll29 ; CHECK-NEXT: [[CMP1:%.*]] = fcmp ord double [[B:%.*]], 0.000000e+00
30 ; CHECK-NEXT: [[AND:%.*]] = and i1 [[CMP]], [[CMP1]]
42 ; CHECK-NEXT: [[CMP1:%.*]] = fcmp ord <2 x double> [[B:%.*]], zeroinitializer
43 ; CHECK-NEXT: [[AND:%.*]] = and <2 x i1> [[CMP]], [[CMP1]]
1366 ; CHECK-NEXT: [[CMP1:%.*]] = fcmp oeq double [[A:%.*]], [[B:%.*]]
1367 ; CHECK-NEXT: ret i1 [[CMP1]]
1377 ; CHECK-NEXT: [[CMP1:%.*]] = fcmp ogt double [[A:%.*]], [[B:%.*]]
1378 ; CHECK-NEXT: ret i1 [[CMP1]]
1388 ; CHECK-NEXT: [[CMP1:%.*]] = fcmp oge double [[A:%.*]], [[B:%.*]]
1389 ; CHECK-NEXT: ret i1 [[CMP1]]
[all …]
Dsdiv-guard.ll9 ; CHECK-NEXT: [[CMP1:%.*]] = icmp ne i32 [[X:%.*]], 0
10 ; CHECK-NEXT: [[CMP:%.*]] = and i1 [[CMP1]], [[FLAG:%.*]]
Dsmin-icmp.ll139 ; CHECK-NEXT: [[CMP1:%.*]] = icmp slt i32 %y, %x
140 ; CHECK-NEXT: ret i1 [[CMP1]]
168 ; CHECK-NEXT: [[CMP1:%.*]] = icmp sgt i32 [[X]], %y
169 ; CHECK-NEXT: ret i1 [[CMP1]]
195 ; CHECK-NEXT: [[CMP1:%.*]] = icmp slt i32 %y, %x
196 ; CHECK-NEXT: ret i1 [[CMP1]]
224 ; CHECK-NEXT: [[CMP1:%.*]] = icmp sgt i32 [[X]], %y
225 ; CHECK-NEXT: ret i1 [[CMP1]]
Dnarrow.ll114 ; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i32 [[LD]], [[NEEDLE:%.*]]
115 ; CHECK-NEXT: [[ZEXT:%.*]] = zext i1 [[CMP1]] to i8
157 ; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i32 [[LD]], [[HAY:%.*]]
158 ; CHECK-NEXT: [[ZEXT:%.*]] = zext i1 [[CMP1]] to i8
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/InstSimplify/
Dand-icmps-same-ops.ll9 ; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i8 %a, %b
10 ; CHECK-NEXT: ret i1 [[CMP1]]
30 ; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i8 %a, %b
31 ; CHECK-NEXT: ret i1 [[CMP1]]
51 ; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i8 %a, %b
52 ; CHECK-NEXT: ret i1 [[CMP1]]
72 ; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i8 %a, %b
73 ; CHECK-NEXT: ret i1 [[CMP1]]
93 ; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i8 %a, %b
94 ; CHECK-NEXT: ret i1 [[CMP1]]
[all …]
Dor-icmps-same-ops.ll41 ; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i8 %a, %b
43 ; CHECK-NEXT: [[OR:%.*]] = or i1 [[CMP1]], [[CMP2]]
65 ; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i8 %a, %b
67 ; CHECK-NEXT: [[OR:%.*]] = or i1 [[CMP1]], [[CMP2]]
89 ; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i8 %a, %b
91 ; CHECK-NEXT: [[OR:%.*]] = or i1 [[CMP1]], [[CMP2]]
113 ; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i8 %a, %b
115 ; CHECK-NEXT: [[OR:%.*]] = or i1 [[CMP1]], [[CMP2]]
159 ; CHECK-NEXT: [[CMP1:%.*]] = icmp ne i8 %a, %b
160 ; CHECK-NEXT: ret i1 [[CMP1]]
[all …]
Dlogic-of-fcmps.ll52 ; CHECK-NEXT: [[CMP1:%.*]] = fcmp ord float %x, %y
53 ; CHECK-NEXT: ret i1 [[CMP1]]
64 ; CHECK-NEXT: [[CMP1:%.*]] = fcmp ord double %y, %x
65 ; CHECK-NEXT: ret i1 [[CMP1]]
75 ; CHECK-NEXT: [[CMP1:%.*]] = fcmp ord <2 x float> %x, %y
76 ; CHECK-NEXT: ret <2 x i1> [[CMP1]]
86 ; CHECK-NEXT: [[CMP1:%.*]] = fcmp ord <2 x double> %y, %x
87 ; CHECK-NEXT: ret <2 x i1> [[CMP1]]
141 ; CHECK-NEXT: [[CMP1:%.*]] = fcmp uno float %x, %y
142 ; CHECK-NEXT: ret i1 [[CMP1]]
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/EarlyCSE/
Dcommute.ll78 ; CHECK-NEXT: [[CMP1:%.*]] = icmp slt i8 %a, %b
80 ; CHECK-NEXT: [[M1:%.*]] = select i1 [[CMP1]], i8 %a, i8 %b
96 ; CHECK-NEXT: [[CMP1:%.*]] = icmp sgt i8 %a, %b
98 ; CHECK-NEXT: [[M1:%.*]] = select i1 [[CMP1]], i8 %b, i8 %a
111 ; CHECK-NEXT: [[CMP1:%.*]] = icmp sgt i8 %a, %b
113 ; CHECK-NEXT: [[M1:%.*]] = select i1 [[CMP1]], i8 %a, i8 %b
126 ; CHECK-NEXT: [[CMP1:%.*]] = icmp slt i8 %a, %b
128 ; CHECK-NEXT: [[M1:%.*]] = select i1 [[CMP1]], i8 %b, i8 %a
141 ; CHECK-NEXT: [[CMP1:%.*]] = icmp ult i8 %a, %b
143 ; CHECK-NEXT: [[M1:%.*]] = select i1 [[CMP1]], i8 %a, i8 %b
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/
Dselect-opt.ll9 ; GCN-DAG: v_cmp_ne_u32_e64 [[CMP1:s\[[0-9]+:[0-9]+\]]]
10 ; GCN: s_and_b64 vcc, vcc, [[CMP1]]
25 ; GCN-DAG: v_cmp_lg_f32_e64 [[CMP1:s\[[0-9]+:[0-9]+\]]]
26 ; GCN: s_and_b64 vcc, vcc, [[CMP1]]
41 ; GCN-DAG: v_cmp_ne_u32_e64 [[CMP1:s\[[0-9]+:[0-9]+\]]]
42 ; GCN: s_and_b64 vcc, vcc, [[CMP1]]
57 ; GCN-DAG: v_cmp_lg_f32_e64 [[CMP1:s\[[0-9]+:[0-9]+\]]]
58 ; GCN: s_and_b64 vcc, vcc, [[CMP1]]
73 ; GCN-DAG: v_cmp_ne_u32_e64 [[CMP1:s\[[0-9]+:[0-9]+\]]]
74 ; GCN: s_or_b64 vcc, vcc, [[CMP1]]
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/
Dcmpxchg-O0.ll21 ; CHECK: uxtb [[CMP1:r[0-9]+]], [[DESIRED]]
22 ; CHECK: sub{{(s)?}} [[CMP1]], [[OLD]], [[CMP1]]
23 ; CHECK: clz [[CMP2:r[0-9]+]], [[CMP1]]
43 ; CHECK: uxth [[CMP1:r[0-9]+]], [[DESIRED]]
44 ; CHECK: sub{{(s)?}} [[CMP1]], [[OLD]], [[CMP1]]
45 ; CHECK: clz [[CMP2:r[0-9]+]], [[CMP1]]
65 ; CHECK: sub{{(s)?}} [[CMP1:r[0-9]+]], [[OLD]], [[DESIRED]]
66 ; CHECK: clz [[CMP2:r[0-9]+]], [[CMP1]]
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/IRCE/
Dranges_of_different_types.ll27 ; CHECK-NEXT: [[CMP1:%[^ ]+]] = icmp sgt i32 [[SUB1]], -102
28 ; CHECK-NEXT: [[SMAX:%[^ ]+]] = select i1 [[CMP1]], i32 [[SUB1]], i32 -102
84 ; CHECK-NEXT: [[CMP1:%[^ ]+]] = icmp sgt i32 [[LEN_MINUS_SMAX]], -13
85 ; CHECK-NEXT: [[SMAX1:%[^ ]+]] = select i1 [[CMP1]], i32 [[LEN_MINUS_SMAX]], i32 -13
156 ; CHECK-NEXT: [[CMP1:%[^ ]+]] = icmp sgt i32 [[SUB2]], -14
157 ; CHECK-NEXT: [[SMAX1:%[^ ]+]] = select i1 [[CMP1]], i32 [[SUB2]], i32 -14
212 ; CHECK-NEXT: [[CMP1:%[^ ]+]] = icmp ugt i32 [[SUB1]], -102
213 ; CHECK-NEXT: [[UMAX1:%[^ ]+]] = select i1 [[CMP1]], i32 [[SUB1]], i32 -102
256 ; CHECK-NEXT: [[CMP1:%[^ ]+]] = icmp sgt i32 [[SUB1]], -102
257 ; CHECK-NEXT: [[SMAX:%[^ ]+]] = select i1 [[CMP1]], i32 [[SUB1]], i32 -102
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/SLPVectorizer/AMDGPU/
Dhorizontal-store.ll21 ; GFX9-NEXT: [[CMP1:%.*]] = icmp sgt i32 [[TMP2]], [[TMP3]]
22 ; GFX9-NEXT: [[SELECT1:%.*]] = select i1 [[CMP1]], i32 [[TMP2]], i32 [[TMP3]]
33 ; GFX9-NEXT: [[STORE_SELECT:%.*]] = select i1 [[CMP1]], i32 3, i32 4
68 ; GFX9-NEXT: [[CMP1:%.*]] = icmp slt i64 [[TMP2]], [[TMP3]]
69 ; GFX9-NEXT: [[SELECT1:%.*]] = select i1 [[CMP1]], i64 [[TMP2]], i64 [[TMP3]]
80 ; GFX9-NEXT: [[STORE_SELECT:%.*]] = select i1 [[CMP1]], i64 3, i64 4
115 ; GFX9-NEXT: [[CMP1:%.*]] = fcmp fast ogt float [[TMP2]], [[TMP3]]
116 ; GFX9-NEXT: [[SELECT1:%.*]] = select i1 [[CMP1]], float [[TMP2]], float [[TMP3]]
127 ; GFX9-NEXT: [[STORE_SELECT:%.*]] = select i1 [[CMP1]], float 3.000000e+00, float 4.000000e+00
162 ; GFX9-NEXT: [[CMP1:%.*]] = fcmp fast olt double [[TMP2]], [[TMP3]]
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/NewGVN/
Dphi-of-ops-move-block.ll17 ; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i64 [[LV]], 0
18 ; CHECK-NEXT: br i1 [[CMP1]], label [[PREHEADER_SPLIT:%.*]], label [[CRITEDGE]]
65 ; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i32 [[STOREMERGE]], 0
66 ; CHECK-NEXT: br i1 [[CMP1]], label [[LR_PH:%.*]], label [[CRITEDGE]]
75 ; CHECK-NEXT: [[PHIOFOPS:%.*]] = phi i1 [ [[CMP1]], [[BB1]] ], [ true, [[SPLIT2]] ], [ true, [[S…
/external/llvm/test/Transforms/InstCombine/
Dand-fcmp.ll8 ; CHECK-NEXT: [[CMP1:%.*]] = fcmp ord double %b, 0.000000e+00
9 ; CHECK-NEXT: [[AND:%.*]] = and i1 [[CMP]], [[CMP1]]
21 ; CHECK-NEXT: [[CMP1:%.*]] = fcmp ord <2 x double> %b, zeroinitializer
22 ; CHECK-NEXT: [[AND:%.*]] = and <2 x i1> [[CMP]], [[CMP1]]
1323 ; CHECK-NEXT: [[CMP1:%.*]] = fcmp oeq double %a, %b
1324 ; CHECK-NEXT: ret i1 [[CMP1]]
1334 ; CHECK-NEXT: [[CMP1:%.*]] = fcmp ogt double %a, %b
1335 ; CHECK-NEXT: ret i1 [[CMP1]]
1345 ; CHECK-NEXT: [[CMP1:%.*]] = fcmp oge double %a, %b
1346 ; CHECK-NEXT: ret i1 [[CMP1]]
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/SimplifyCFG/
Dmultiple-phis.ll23 ; CHECK-NEXT: [[CMP1:%.*]] = icmp ult i32 [[K:%.*]], [[TMP0]]
25 ; CHECK-NEXT: [[DIV_HIGH_ADDR_0]] = select i1 [[CMP1]], i32 [[DIV]], i32 [[HIGH_ADDR_0]]
26 ; CHECK-NEXT: [[LOW_0_ADD2]] = select i1 [[CMP1]], i32 [[LOW_0]], i32 [[ADD2]]
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/LoopUnroll/
Dpeel-loop.ll10 ; CHECK: %[[CMP1:.*]] = icmp eq i32 %k, 1
11 ; CHECK: br i1 %[[CMP1]], label %for.end, label %[[NEXT1:.*]]
57 ; CHECK: %[[CMP1:.*]] = icmp eq i32 %k, 1
58 ; CHECK: br i1 %[[CMP1]], label %for.end, label %[[NEXT1:.*]]
Dpeel-loop-conditions.ll349 ; CHECK-NEXT: [[CMP1:%.*]] = icmp ugt i32 [[I_05]], 9999
350 ; CHECK-NEXT: br i1 [[CMP1]], label [[IF_THEN:%.*]], label [[FOR_INC]]
393 ; CHECK-NEXT: [[CMP1:%.*]] = icmp ult i32 [[J]], 2
394 ; CHECK-NEXT: br i1 [[CMP1]], label [[IF_THEN:%.*]], label [[IF_ELSE:%.*]]
457 ; CHECK-NEXT: [[CMP1:%.*]] = icmp ult i32 [[I_05]], [[J]]
458 ; CHECK-NEXT: br i1 [[CMP1]], label [[IF_THEN:%.*]], label [[IF_ELSE:%.*]]
508 ; CHECK-NEXT: [[CMP1:%.*]] = icmp ne i32 [[I_05]], 3
509 ; CHECK-NEXT: br i1 [[CMP1]], label [[IF_THEN:%.*]], label [[FOR_INC]]
549 ; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i32 [[I_05]], 3
550 ; CHECK-NEXT: br i1 [[CMP1]], label [[IF_THEN:%.*]], label [[FOR_INC]]
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/IndVarSimplify/
Div-widen-elim-ext.ll12 ; CHECK-NEXT: [[CMP1:%.*]] = icmp slt i32 0, %N
13 ; CHECK-NEXT: br i1 [[CMP1]], label %for.body.lr.ph, label %for.end
79 ; CHECK-NEXT: [[CMP1:%.*]] = icmp slt i32 0, %N
80 ; CHECK-NEXT: br i1 [[CMP1]], label %for.body.lr.ph, label %for.end
145 ; CHECK-NEXT: [[CMP1:%.*]] = icmp slt i32 0, %M
146 ; CHECK-NEXT: br i1 [[CMP1]], label %for.body.lr.ph, label %for.end
213 ; CHECK-NEXT: [[CMP1:%.*]] = icmp slt i32 0, %M
214 ; CHECK-NEXT: br i1 [[CMP1]], label %for.body.lr.ph, label %for.end
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/SLPVectorizer/X86/
Dvector.ll27 ; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i32 [[X1]], [[Y1]]
30 ; CHECK-NEXT: [[AND_OF_CMPS:%.*]] = phi i1 [ false, [[ENTRY:%.*]] ], [ [[CMP1]], [[IF]] ]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/PowerPC/
DmemcmpIR.ll62 ; CHECK-NEXT: [[CMP1:%[0-9]+]] = icmp ugt i32 [[BSWAP1]], [[BSWAP2]]
64 ; CHECK-NEXT: [[Z1:%[0-9]+]] = zext i1 [[CMP1]] to i32
72 ; CHECK-BE-NEXT: [[CMP1:%[0-9]+]] = icmp ugt i32 [[LOAD1]], [[LOAD2]]
74 ; CHECK-BE-NEXT: [[Z1:%[0-9]+]] = zext i1 [[CMP1]] to i32

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