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Searched refs:CONFIG_SYS_DDR_TIMING_4 (Results 1 – 18 of 18) sorted by relevance

/external/u-boot/board/freescale/corenet_ds/
Dp4080ds_ddr.c66 #define CONFIG_SYS_DDR_TIMING_4 0x00000001 macro
101 .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
133 .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
165 .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
197 .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
229 .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
261 .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
293 .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
325 .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
/external/u-boot/include/configs/
DBSC9132QDS.h178 #define CONFIG_SYS_DDR_TIMING_4 CONFIG_SYS_DDR_TIMING_4_800 macro
184 #define CONFIG_SYS_DDR_TIMING_4 CONFIG_SYS_DDR_TIMING_4_1333 macro
190 #define CONFIG_SYS_DDR_TIMING_4 CONFIG_SYS_DDR_TIMING_4_800 macro
DBSC9131RDB.h99 #define CONFIG_SYS_DDR_TIMING_4 0x00000001 macro
Dp1_twr.h100 #define CONFIG_SYS_DDR_TIMING_4 0x00220001 macro
DMPC8569MDS.h103 #define CONFIG_SYS_DDR_TIMING_4 0x00220001 macro
DUCP1020.h176 #define CONFIG_SYS_DDR_TIMING_4 0x00220001 macro
DP1022DS.h163 #define CONFIG_SYS_DDR_TIMING_4 0x00220001 macro
DP1010RDB.h238 #define CONFIG_SYS_DDR_TIMING_4 0x00000001 macro
Dp1_p2_rdb_pc.h314 #define CONFIG_SYS_DDR_TIMING_4 0x00220001 macro
/external/u-boot/board/freescale/bsc9132qds/
Dddr.c35 .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
62 .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
/external/u-boot/board/freescale/p1010rdb/
Dddr.c38 .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
65 .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
/external/u-boot/board/freescale/p1_twr/
Dddr.c44 .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4, in fixed_sdram()
/external/u-boot/board/freescale/bsc9131rdb/
Dspl_minimal.c45 __raw_writel(CONFIG_SYS_DDR_TIMING_4, &ddr->timing_cfg_4); in sdram_init()
Dddr.c36 .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
/external/u-boot/board/Arcturus/ucp1020/
Dddr.c104 .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4, in fixed_sdram()
/external/u-boot/board/freescale/p1_p2_rdb_pc/
Dddr.c236 .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4, in fixed_sdram()
/external/u-boot/board/freescale/mpc8569mds/
Dmpc8569mds.c251 out_be32(&ddr->timing_cfg_4, CONFIG_SYS_DDR_TIMING_4); in fixed_sdram()
/external/u-boot/scripts/
Dconfig_whitelist.txt2495 CONFIG_SYS_DDR_TIMING_4