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Searched refs:CONFIG_SYS_FSL_OCRAM_BASE (Results 1 – 10 of 10) sorted by relevance

/external/u-boot/arch/arm/include/asm/arch-fsl-layerscape/
Dcpu.h101 { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
156 { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
200 { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
306 { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
Dconfig.h31 #define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */ macro
175 #define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */ macro
180 #define CONFIG_SYS_FSL_OCRAM_BASE 0x10000000 /* initial RAM */ macro
/external/u-boot/include/configs/
Dls2080a_common.h20 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
209 #define CONFIG_SPL_STACK (CONFIG_SYS_FSL_OCRAM_BASE + 0x9ff0)
Dls1088a_common.h32 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
228 #define CONFIG_SPL_STACK (CONFIG_SYS_FSL_OCRAM_BASE + 0x9ff0)
Dls1012a_common.h19 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
Dls1046a_common.h35 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
Dls1043a_common.h37 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
/external/u-boot/arch/arm/cpu/armv8/fsl-layerscape/
Dlowlevel.S317 ldr x0, =CONFIG_SYS_FSL_OCRAM_BASE
318 ldr x1, =(CONFIG_SYS_FSL_OCRAM_BASE + CONFIG_SYS_FSL_OCRAM_SIZE)
Dcpu.c77 gd->arch.tlb_addr = CONFIG_SYS_FSL_OCRAM_BASE; in early_mmu_setup()
/external/u-boot/scripts/
Dconfig_whitelist.txt2882 CONFIG_SYS_FSL_OCRAM_BASE