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Searched refs:CONFIG_SYS_PCI1_IO_PHYS (Results 1 – 25 of 39) sorted by relevance

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/external/u-boot/board/freescale/mpc832xemds/
Dpci.c27 phys_start: CONFIG_SYS_PCI1_IO_PHYS,
74 pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR; in pci_init_board()
132 pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
/external/u-boot/board/freescale/mpc8349emds/
Dpci.c23 phys_start: CONFIG_SYS_PCI1_IO_PHYS,
138 pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR; in pci_init_board()
162 pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR; in pci_init_board()
/external/u-boot/board/sbc8349/
Dpci.c27 phys_start: CONFIG_SYS_PCI1_IO_PHYS,
62 pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR; in pci_init_board()
/external/u-boot/board/tqc/tqm834x/
Dpci.c25 phys_start: CONFIG_SYS_PCI1_IO_PHYS,
90 pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR; in pci_init_board()
/external/u-boot/board/xes/xpedite520x/
Dtlb.c62 SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_IO_PHYS, CONFIG_SYS_PCI1_IO_PHYS,
/external/u-boot/board/freescale/mpc8349itx/
Dpci.c24 phys_start: CONFIG_SYS_PCI1_IO_PHYS,
92 pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR; in pci_init_board()
/external/u-boot/board/esd/vme8349/
Dpci.c31 phys_start: CONFIG_SYS_PCI1_IO_PHYS,
101 pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR; in pci_init_board()
/external/u-boot/board/freescale/mpc8313erdb/
Dmpc8313erdb.c69 .phys_start = CONFIG_SYS_PCI1_IO_PHYS,
91 pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR; in pci_init_board()
/external/u-boot/include/configs/
DMPC8610HPCD.h235 #define CONFIG_SYS_PCI1_IO_PHYS 0xe1000000 macro
315 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \
318 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
DMPC8548CDS.h343 #define CONFIG_SYS_PCI1_IO_PHYS 0xfe2000000ull macro
345 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 macro
DMPC8349ITX.h373 #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 macro
387 (CONFIG_SYS_PCI1_IO_PHYS + CONFIG_SYS_PCI1_IO_SIZE)
DMPC8536DS.h403 #define CONFIG_SYS_PCI1_IO_PHYS 0xfffc00000ull macro
405 #define CONFIG_SYS_PCI1_IO_PHYS 0xffc00000 macro
DMPC8541CDS.h267 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 macro
DMPC8555CDS.h265 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 macro
DMPC8540ADS.h241 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 macro
Dsocrates.h216 #define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE macro
DMPC8568MDS.h242 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 macro
/external/u-boot/board/freescale/mpc8323erdb/
Dmpc8323erdb.c152 phys_start: CONFIG_SYS_PCI1_IO_PHYS,
172 pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR; in pci_init_board()
/external/u-boot/arch/powerpc/cpu/mpc85xx/
Dpci.c91 pcix->powbar2 = (CONFIG_SYS_PCI1_IO_PHYS >> 12) & 0x000fffff; in pci_mpc85xx_init()
114 CONFIG_SYS_PCI1_IO_PHYS, in pci_mpc85xx_init()
/external/u-boot/board/ve8313/
Dve8313.c166 phys_start: CONFIG_SYS_PCI1_IO_PHYS,
188 out_be32(&pci_law[1].bar, CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR); in pci_init_board()
/external/u-boot/board/freescale/mpc8555cds/
Dlaw.c35 SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI),
/external/u-boot/board/freescale/mpc8541cds/
Dlaw.c35 SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI),
/external/u-boot/board/socrates/
Dlaw.c36 SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI),
/external/u-boot/board/freescale/mpc8548cds/
Dtlb.c73 SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_IO_VIRT, CONFIG_SYS_PCI1_IO_PHYS,
/external/u-boot/board/freescale/mpc8536ds/
Dtlb.c49 SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_IO_VIRT, CONFIG_SYS_PCI1_IO_PHYS,

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