/external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
D | ARMInstrInfo.td | 4215 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2), 4216 NoItinerary, "cdp", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2", 4217 [(int_arm_cdp imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn, 4221 bits<4> CRd; 4230 let Inst{15-12} = CRd; 4236 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2), 4237 NoItinerary, "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2", 4238 [(int_arm_cdp2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn, 4243 bits<4> CRd; 4252 let Inst{15-12} = CRd; [all …]
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D | ARMInstrThumb2.td | 3451 (outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr), 3452 asm, "\t$cop, $CRd, $addr"> { 3455 bits<4> CRd; 3462 let Inst{15-12} = CRd; 3468 (outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr), 3469 asm, "\t$cop, $CRd, $addr!"> { 3472 bits<4> CRd; 3479 let Inst{15-12} = CRd; 3485 (outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr, 3487 asm, "\t$cop, $CRd, $addr, $offset"> { [all …]
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
D | ARMInstrInfo.td | 5079 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2), 5080 NoItinerary, "cdp", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2", 5081 [(int_arm_cdp imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn, 5086 bits<4> CRd; 5095 let Inst{15-12} = CRd; 5103 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2), 5104 NoItinerary, "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2", 5105 [(int_arm_cdp2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn, 5111 bits<4> CRd; 5120 let Inst{15-12} = CRd; [all …]
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D | ARMInstrThumb2.td | 3926 (outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr), 3927 asm, "\t$cop, $CRd, $addr", pattern> { 3930 bits<4> CRd; 3937 let Inst{15-12} = CRd; 3943 (outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5_pre:$addr), 3944 asm, "\t$cop, $CRd, $addr!", []> { 3947 bits<4> CRd; 3954 let Inst{15-12} = CRd; 3960 (outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr, 3962 asm, "\t$cop, $CRd, $addr, $offset", []> { [all …]
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/external/llvm/lib/Target/ARM/ |
D | ARMInstrInfo.td | 4813 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2), 4814 NoItinerary, "cdp", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2", 4815 [(int_arm_cdp imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn, 4820 bits<4> CRd; 4829 let Inst{15-12} = CRd; 4835 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2), 4836 NoItinerary, "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2", 4837 [(int_arm_cdp2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn, 4843 bits<4> CRd; 4852 let Inst{15-12} = CRd; [all …]
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D | ARMInstrThumb2.td | 3936 (outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr), 3937 asm, "\t$cop, $CRd, $addr", pattern> { 3940 bits<4> CRd; 3947 let Inst{15-12} = CRd; 3953 (outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5_pre:$addr), 3954 asm, "\t$cop, $CRd, $addr!", []> { 3957 bits<4> CRd; 3964 let Inst{15-12} = CRd; 3970 (outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr, 3972 asm, "\t$cop, $CRd, $addr, $offset", []> { [all …]
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/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/ARM/ |
D | ARMGenDAGISel.inc | 10025 /* 21345*/ OPC_RecordChild4, // #3 = $CRd 10054 …TR] }, (imm:{ *:[i32] }):$cop, (imm:{ *:[i32] }):$opc1, (imm:{ *:[i32] }):$CRd, (imm:{ *:[i32] }):… 10055 …: (CDP (imm:{ *:[i32] }):$cop, (imm:{ *:[i32] }):$opc1, (imm:{ *:[i32] }):$CRd, (imm:{ *:[i32] }):… 10069 …TR] }, (imm:{ *:[i32] }):$cop, (imm:{ *:[i32] }):$opc1, (imm:{ *:[i32] }):$CRd, (imm:{ *:[i32] }):… 10070 …(t2CDP (imm:{ *:[i32] }):$cop, (imm:{ *:[i32] }):$opc1, (imm:{ *:[i32] }):$CRd, (imm:{ *:[i32] }):… 10082 /* 21457*/ OPC_RecordChild4, // #3 = $CRd 10109 …TR] }, (imm:{ *:[i32] }):$cop, (imm:{ *:[i32] }):$opc1, (imm:{ *:[i32] }):$CRd, (imm:{ *:[i32] }):… 10110 … (CDP2 (imm:{ *:[i32] }):$cop, (imm:{ *:[i32] }):$opc1, (imm:{ *:[i32] }):$CRd, (imm:{ *:[i32] }):… 10124 …TR] }, (imm:{ *:[i32] }):$cop, (imm:{ *:[i32] }):$opc1, (imm:{ *:[i32] }):$CRd, (imm:{ *:[i32] }):… 10125 …t2CDP2 (imm:{ *:[i32] }):$cop, (imm:{ *:[i32] }):$opc1, (imm:{ *:[i32] }):$CRd, (imm:{ *:[i32] }):… [all …]
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D | ARMGenMCCodeEmitter.inc | 8050 // op: CRd 8398 // op: CRd 8412 // op: CRd 8465 // op: CRd 10107 // op: CRd 10182 // op: CRd 10203 // op: CRd 10803 // op: CRd
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D | ARMGenGlobalISel.inc | 20526 …CRd, (imm:{ *:[i32] }):$CRn, (imm:{ *:[i32] }):$CRm, (imm:{ *:[i32] }):$opc2) => (CDP (imm:{ *:[… 20530 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // CRd 20581 …CRd, (imm:{ *:[i32] }):$CRn, (imm:{ *:[i32] }):$CRm, (imm:{ *:[i32] }):$opc2) => (CDP2 (imm:{ *:… 20585 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // CRd 20634 …CRd, (imm:{ *:[i32] }):$CRn, (imm:{ *:[i32] }):$CRm, (imm:{ *:[i32] }):$opc2) => (t2CDP (imm:{ *… 20638 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // CRd 20689 …CRd, (imm:{ *:[i32] }):$CRn, (imm:{ *:[i32] }):$CRm, (imm:{ *:[i32] }):$opc2) => (t2CDP2 (imm:{ … 20693 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // CRd
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/external/honggfuzz/examples/apache-httpd/corpus_http1/ |
D | 11eed1760d4ac87ca521bab29af44a5b.000127c6.honggfuzz.cov | 238 �X�?4���;Ȥ+�?��\�?���%����7)ȱu� ��:Z,ۣ��g�Yd<d�!�^���e.�lo����W����`�<����*�7�S�CRd�;��Ă… 370 �X�?4���;Ȥ+�?��\�?���%����7)ȱu� ��:Z,ۣ��g�Yd<d�!�^���e.�lo����W����`�<����*�7�S�CRd�;��Ă… 480 �X�?4���;Ȥ+�?��\�?���%����7)ȱu� ��:Z,ۣ��g�Yd<d�!�^���e.�lo����W����`�<����*�7�S�CRd�;��Ă…
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/external/honggfuzz/examples/apache-httpd/corpus_http2/ |
D | 11eed1760d4ac87ca521bab29af44a5b.000127c6.honggfuzz.cov | 238 �X�?4���;Ȥ+�?��\�?���%����7)ȱu� ��:Z,ۣ��g�Yd<d�!�^���e.�lo����W����`�<����*�7�S�CRd�;��Ă… 370 �X�?4���;Ȥ+�?��\�?���%����7)ȱu� ��:Z,ۣ��g�Yd<d�!�^���e.�lo����W����`�<����*�7�S�CRd�;��Ă… 480 �X�?4���;Ȥ+�?��\�?���%����7)ȱu� ��:Z,ۣ��g�Yd<d�!�^���e.�lo����W����`�<����*�7�S�CRd�;��Ă…
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D | fd1b1b2cc4dcd8b879282abd6831c99c.0001fec7.honggfuzz.cov | 506 �X�?4���;Ȥ+�?��\�?���%����7)ȱu� ��:Z,ۣ��g�Yd<d�!�^���e.�lo����W����`�<����*�7�S�CRd�;��Ă…
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/external/capstone/arch/ARM/ |
D | ARMDisassembler.c | 1372 unsigned CRd = fieldFromInstruction_4(Insn, 12, 4); in DecodeCopMemInstruction() local 1419 MCOperand_CreateImm0(Inst, CRd); in DecodeCopMemInstruction()
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/external/swiftshader/third_party/LLVM/lib/Target/ARM/Disassembler/ |
D | ARMDisassembler.cpp | 1186 unsigned CRd = fieldFromInstruction32(Insn, 12, 4); in DecodeCopMemInstruction() local 1233 Inst.addOperand(MCOperand::CreateImm(CRd)); in DecodeCopMemInstruction()
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/external/llvm/lib/Target/ARM/Disassembler/ |
D | ARMDisassembler.cpp | 1326 unsigned CRd = fieldFromInstruction(Insn, 12, 4); in DecodeCopMemInstruction() local 1378 Inst.addOperand(MCOperand::createImm(CRd)); in DecodeCopMemInstruction()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/Disassembler/ |
D | ARMDisassembler.cpp | 1325 unsigned CRd = fieldFromInstruction(Insn, 12, 4); in DecodeCopMemInstruction() local 1377 Inst.addOperand(MCOperand::createImm(CRd)); in DecodeCopMemInstruction()
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