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Searched refs:CS4BCR (Results 1 – 13 of 13) sorted by relevance

/external/u-boot/arch/sh/include/asm/
Dcpu_sh7710.h27 #define CS4BCR 0xA4FD0010 macro
Dcpu_sh7785.h47 #define CS4BCR (LBSC_BASE + 0x2040) macro
Dcpu_sh7723.h38 #define CS4BCR 0xFEC10010 macro
Dcpu_sh7724.h39 #define CS4BCR 0xFEC10010 macro
Dcpu_sh7720.h64 #define CS4BCR (BSC_BASE + 0x10) macro
Dcpu_sh7780.h81 #define CS4BCR 0xFF802040 macro
Dcpu_sh7722.h128 #define CS4BCR 0xFEC10010 macro
/external/u-boot/board/mpr2/
Dmpr2.c30 __raw_writel(0x00000200, CS4BCR); /* no idle cycles, normal space, 8 bit data bus */ in board_init()
/external/u-boot/board/renesas/ap325rxa/
Dlowlevel_init.S140 CS4BCR_A: .long CS4BCR
/external/u-boot/board/ms7722se/
Dlowlevel_init.S180 CS4BCR_A: .long CS4BCR ! FPGA, PCMCIA, USB, ext slot
/external/u-boot/board/renesas/MigoR/
Dlowlevel_init.S148 CS4BCR_A: .long CS4BCR
/external/u-boot/board/renesas/r7780mp/
Dlowlevel_init.S326 CS4BCR_A: .long CS4BCR
/external/u-boot/board/renesas/sh7785lcr/
Dlowlevel_init.S283 CS4BCR_A: .long CS4BCR