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Searched refs:CS5ABCR (Results 1 – 9 of 9) sorted by relevance

/external/u-boot/arch/sh/include/asm/
Dcpu_sh7710.h28 #define CS5ABCR 0xA4FD0014 macro
Dcpu_sh7723.h39 #define CS5ABCR 0xFEC10014 macro
Dcpu_sh7724.h40 #define CS5ABCR 0xFEC10014 macro
Dcpu_sh7720.h65 #define CS5ABCR (BSC_BASE + 0x14) macro
Dcpu_sh7722.h129 #define CS5ABCR 0xFEC10014 macro
/external/u-boot/board/mpr2/
Dmpr2.c34 __raw_writel(0x00000200, CS5ABCR); /* no idle cycles, normal space, 8 bit data bus */ in board_init()
/external/u-boot/board/renesas/ap325rxa/
Dlowlevel_init.S141 CS5ABCR_A: .long CS5ABCR
/external/u-boot/board/ms7722se/
Dlowlevel_init.S182 CS5ABCR_A: .long CS5ABCR ! Ext slot
/external/u-boot/board/renesas/MigoR/
Dlowlevel_init.S150 CS5ABCR_A: .long CS5ABCR