Searched refs:CombineOpc (Results 1 – 4 of 4) sorted by relevance
1735 unsigned CombineOpc = 0; in SplitVecOp_VECREDUCE() local1737 case ISD::VECREDUCE_FADD: CombineOpc = ISD::FADD; break; in SplitVecOp_VECREDUCE()1738 case ISD::VECREDUCE_FMUL: CombineOpc = ISD::FMUL; break; in SplitVecOp_VECREDUCE()1739 case ISD::VECREDUCE_ADD: CombineOpc = ISD::ADD; break; in SplitVecOp_VECREDUCE()1740 case ISD::VECREDUCE_MUL: CombineOpc = ISD::MUL; break; in SplitVecOp_VECREDUCE()1741 case ISD::VECREDUCE_AND: CombineOpc = ISD::AND; break; in SplitVecOp_VECREDUCE()1742 case ISD::VECREDUCE_OR: CombineOpc = ISD::OR; break; in SplitVecOp_VECREDUCE()1743 case ISD::VECREDUCE_XOR: CombineOpc = ISD::XOR; break; in SplitVecOp_VECREDUCE()1744 case ISD::VECREDUCE_SMAX: CombineOpc = ISD::SMAX; break; in SplitVecOp_VECREDUCE()1745 case ISD::VECREDUCE_SMIN: CombineOpc = ISD::SMIN; break; in SplitVecOp_VECREDUCE()[all …]
2851 unsigned CombineOpc, unsigned ZeroReg = 0, in canCombine() argument2859 if (!MI || MI->getParent() != &MBB || (unsigned)MI->getOpcode() != CombineOpc) in canCombine()
3560 unsigned CombineOpc, unsigned ZeroReg = 0, in canCombine() argument3568 if (!MI || MI->getParent() != &MBB || (unsigned)MI->getOpcode() != CombineOpc) in canCombine()
18405 unsigned CombineOpc; in LowerVSETCC() local18409 CombineOpc = X86ISD::FOR; in LowerVSETCC()18414 CombineOpc = X86ISD::FAND; in LowerVSETCC()18421 Cmp = DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1); in LowerVSETCC()