| /external/swiftshader/third_party/LLVM/lib/Target/CellSPU/ |
| D | SPUSubtarget.cpp | 53 RegClassVector& CriticalPathRCs) const { in enablePostRAScheduler()
58 CriticalPathRCs.clear(); in enablePostRAScheduler()
59 CriticalPathRCs.push_back(&SPU::R8CRegClass); in enablePostRAScheduler()
60 CriticalPathRCs.push_back(&SPU::R16CRegClass); in enablePostRAScheduler()
61 CriticalPathRCs.push_back(&SPU::R32CRegClass); in enablePostRAScheduler()
62 CriticalPathRCs.push_back(&SPU::R32FPRegClass); in enablePostRAScheduler()
63 CriticalPathRCs.push_back(&SPU::R64CRegClass); in enablePostRAScheduler()
64 CriticalPathRCs.push_back(&SPU::VECREGRegClass); in enablePostRAScheduler()
|
| D | SPUSubtarget.h | 93 RegClassVector& CriticalPathRCs) const;
|
| /external/swiftshader/third_party/LLVM/lib/Target/MBlaze/ |
| D | MBlazeSubtarget.cpp | 58 RegClassVector& CriticalPathRCs) const { in enablePostRAScheduler()
60 CriticalPathRCs.clear(); in enablePostRAScheduler()
61 CriticalPathRCs.push_back(&MBlaze::GPRRegClass); in enablePostRAScheduler()
|
| D | MBlazeSubtarget.h | 59 RegClassVector& CriticalPathRCs) const;
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/ |
| D | PostRASchedulerList.cpp | 110 TargetSubtargetInfo::RegClassVector &CriticalPathRCs) const;
151 SmallVectorImpl<const TargetRegisterClass *> &CriticalPathRCs);
210 SmallVectorImpl<const TargetRegisterClass *> &CriticalPathRCs) in SchedulePostRATDList() argument
225 (AntiDepBreaker *)new AggressiveAntiDepBreaker(MF, RCI, CriticalPathRCs) : in SchedulePostRATDList()
270 TargetSubtargetInfo::RegClassVector &CriticalPathRCs) const { in enablePostRAScheduler()
272 ST.getCriticalPathRCs(CriticalPathRCs); in enablePostRAScheduler()
295 SmallVector<const TargetRegisterClass*, 4> CriticalPathRCs; in runOnMachineFunction() local
300 AntiDepMode, CriticalPathRCs)) in runOnMachineFunction()
315 CriticalPathRCs); in runOnMachineFunction()
|
| D | AggressiveAntiDepBreaker.h | 135 TargetSubtargetInfo::RegClassVector& CriticalPathRCs);
|
| D | AggressiveAntiDepBreaker.cpp | 128 TargetSubtargetInfo::RegClassVector &CriticalPathRCs) in AggressiveAntiDepBreaker() argument
134 for (unsigned i = 0, e = CriticalPathRCs.size(); i < e; ++i) { in AggressiveAntiDepBreaker()
135 BitVector CPSet = TRI->getAllocatableSet(MF, CriticalPathRCs[i]); in AggressiveAntiDepBreaker()
|
| /external/llvm/lib/CodeGen/ |
| D | PostRASchedulerList.cpp | 110 TargetSubtargetInfo::RegClassVector &CriticalPathRCs) const;
151 SmallVectorImpl<const TargetRegisterClass *> &CriticalPathRCs);
210 SmallVectorImpl<const TargetRegisterClass *> &CriticalPathRCs) in SchedulePostRATDList() argument
225 (AntiDepBreaker *)new AggressiveAntiDepBreaker(MF, RCI, CriticalPathRCs) : in SchedulePostRATDList()
270 TargetSubtargetInfo::RegClassVector &CriticalPathRCs) const { in enablePostRAScheduler()
272 ST.getCriticalPathRCs(CriticalPathRCs); in enablePostRAScheduler()
295 SmallVector<const TargetRegisterClass*, 4> CriticalPathRCs; in runOnMachineFunction() local
300 AntiDepMode, CriticalPathRCs)) in runOnMachineFunction()
315 CriticalPathRCs); in runOnMachineFunction()
|
| D | AggressiveAntiDepBreaker.h | 129 TargetSubtargetInfo::RegClassVector& CriticalPathRCs);
|
| /external/swiftshader/third_party/LLVM/lib/Target/ |
| D | TargetSubtargetInfo.cpp | 28 RegClassVector& CriticalPathRCs) const { in enablePostRAScheduler()
30 CriticalPathRCs.clear(); in enablePostRAScheduler()
|
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMSubtarget.cpp | 214 RegClassVector& CriticalPathRCs) const { in enablePostRAScheduler()
216 CriticalPathRCs.clear(); in enablePostRAScheduler()
217 CriticalPathRCs.push_back(&ARM::GPRRegClass); in enablePostRAScheduler()
|
| D | ARMSubtarget.h | 253 RegClassVector& CriticalPathRCs) const;
|
| /external/llvm/lib/Target/Mips/ |
| D | MipsSubtarget.cpp | 136 void MipsSubtarget::getCriticalPathRCs(RegClassVector &CriticalPathRCs) const { in getCriticalPathRCs()
137 CriticalPathRCs.clear(); in getCriticalPathRCs()
138 CriticalPathRCs.push_back(isGP64bit() ? in getCriticalPathRCs()
|
| D | MipsSubtarget.h | 167 void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const override;
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/ |
| D | PPCSubtarget.cpp | 189 void PPCSubtarget::getCriticalPathRCs(RegClassVector &CriticalPathRCs) const { in getCriticalPathRCs()
190 CriticalPathRCs.clear(); in getCriticalPathRCs()
191 CriticalPathRCs.push_back(isPPC64() ? in getCriticalPathRCs()
|
| D | PPCSubtarget.h | 322 void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const override;
|
| /external/llvm/lib/Target/PowerPC/ |
| D | PPCSubtarget.cpp | 195 void PPCSubtarget::getCriticalPathRCs(RegClassVector &CriticalPathRCs) const { in getCriticalPathRCs()
196 CriticalPathRCs.clear(); in getCriticalPathRCs()
197 CriticalPathRCs.push_back(isPPC64() ? in getCriticalPathRCs()
|
| D | PPCSubtarget.h | 303 void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const override;
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
| D | MipsSubtarget.cpp | 216 void MipsSubtarget::getCriticalPathRCs(RegClassVector &CriticalPathRCs) const { in getCriticalPathRCs()
217 CriticalPathRCs.clear(); in getCriticalPathRCs()
218 CriticalPathRCs.push_back(isGP64bit() ? &Mips::GPR64RegClass in getCriticalPathRCs()
|
| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| D | PostRASchedulerList.cpp | 142 SmallVectorImpl<TargetRegisterClass*> &CriticalPathRCs);
187 SmallVectorImpl<TargetRegisterClass*> &CriticalPathRCs) in SchedulePostRATDList() argument
197 (AntiDepBreaker *)new AggressiveAntiDepBreaker(MF, RCI, CriticalPathRCs) : in SchedulePostRATDList()
216 SmallVector<TargetRegisterClass*, 4> CriticalPathRCs; in runOnMachineFunction() local
224 if (!ST.enablePostRAScheduler(OptLevel, AntiDepMode, CriticalPathRCs)) in runOnMachineFunction()
240 CriticalPathRCs); in runOnMachineFunction()
|
| D | AggressiveAntiDepBreaker.h | 135 TargetSubtargetInfo::RegClassVector& CriticalPathRCs);
|
| D | AggressiveAntiDepBreaker.cpp | 119 TargetSubtargetInfo::RegClassVector& CriticalPathRCs) : in AggressiveAntiDepBreaker() argument
128 for (unsigned i = 0, e = CriticalPathRCs.size(); i < e; ++i) { in AggressiveAntiDepBreaker()
129 BitVector CPSet = TRI->getAllocatableSet(MF, CriticalPathRCs[i]); in AggressiveAntiDepBreaker()
|
| /external/llvm/include/llvm/Target/ |
| D | TargetSubtargetInfo.h | 169 virtual void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const { in getCriticalPathRCs() argument
170 return CriticalPathRCs.clear(); in getCriticalPathRCs()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/ |
| D | TargetSubtargetInfo.h | 199 virtual void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const { in getCriticalPathRCs() argument
200 return CriticalPathRCs.clear(); in getCriticalPathRCs()
|
| /external/swiftshader/third_party/LLVM/include/llvm/Target/ |
| D | TargetSubtargetInfo.h | 59 RegClassVector& CriticalPathRCs) const;
|