Searched refs:DDR_REG_SEQ2CORE (Results 1 – 1 of 1) sorted by relevance
30 #define DDR_REG_SEQ2CORE 0xFFD0507C macro142 ret = !wait_for_bit_le32((u32 *)DDR_REG_SEQ2CORE, in emif_clear()154 s2c = readl(DDR_REG_SEQ2CORE); in emif_reset()169 if (ddr_wait_bit(DDR_REG_SEQ2CORE, SEQ2CORE_INT_RESP_BIT, 0, 1000000)) { in emif_reset()