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Searched refs:DEF_FIXED (Results 1 – 10 of 10) sorted by relevance

/external/u-boot/drivers/clk/renesas/
Dr8a77990-cpg-mssr.c61 DEF_FIXED(".pll0", CLK_PLL0, CLK_MAIN, 1, 100),
62 DEF_FIXED(".pll0d4", CLK_PLL0D4, CLK_PLL0, 4, 1),
63 DEF_FIXED(".pll0d6", CLK_PLL0D6, CLK_PLL0, 6, 1),
64 DEF_FIXED(".pll0d8", CLK_PLL0D8, CLK_PLL0, 8, 1),
65 DEF_FIXED(".pll0d20", CLK_PLL0D20, CLK_PLL0, 20, 1),
66 DEF_FIXED(".pll0d24", CLK_PLL0D24, CLK_PLL0, 24, 1),
67 DEF_FIXED(".pll1d2", CLK_PLL1D2, CLK_PLL1, 2, 1),
68 DEF_FIXED(".pe", CLK_PE, CLK_PLL0D20, 1, 1),
69 DEF_FIXED(".s0", CLK_S0, CLK_PLL1, 2, 1),
70 DEF_FIXED(".s1", CLK_S1, CLK_PLL1, 3, 1),
[all …]
Dr8a77995-cpg-mssr.c60 DEF_FIXED(".pll0", CLK_PLL0, CLK_MAIN, 4, 250),
61 DEF_FIXED(".pll0d2", CLK_PLL0D2, CLK_PLL0, 2, 1),
62 DEF_FIXED(".pll0d3", CLK_PLL0D3, CLK_PLL0, 3, 1),
63 DEF_FIXED(".pll0d5", CLK_PLL0D5, CLK_PLL0, 5, 1),
64 DEF_FIXED(".pll1d2", CLK_PLL1D2, CLK_PLL1, 2, 1),
65 DEF_FIXED(".pe", CLK_PE, CLK_PLL0D3, 4, 1),
66 DEF_FIXED(".s0", CLK_S0, CLK_PLL1, 2, 1),
67 DEF_FIXED(".s1", CLK_S1, CLK_PLL1, 3, 1),
68 DEF_FIXED(".s2", CLK_S2, CLK_PLL1, 4, 1),
69 DEF_FIXED(".s3", CLK_S3, CLK_PLL1, 6, 1),
[all …]
Dr8a7796-cpg-mssr.c65 DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
66 DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4, CLK_PLL1_DIV2, 2, 1),
67 DEF_FIXED(".s0", CLK_S0, CLK_PLL1_DIV2, 2, 1),
68 DEF_FIXED(".s1", CLK_S1, CLK_PLL1_DIV2, 3, 1),
69 DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1),
70 DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1),
71 DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1),
72 DEF_FIXED(".rpcsrc", CLK_RPCSRC, CLK_PLL1, 2, 1),
75 DEF_FIXED("ztr", R8A7796_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
76 DEF_FIXED("ztrd2", R8A7796_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
[all …]
Dr8a7792-cpg-mssr.c52 DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
58 DEF_FIXED("z", R8A7792_CLK_Z, CLK_PLL0, 1, 1),
59 DEF_FIXED("zg", R8A7792_CLK_ZG, CLK_PLL1, 5, 1),
60 DEF_FIXED("zx", R8A7792_CLK_ZX, CLK_PLL1, 3, 1),
61 DEF_FIXED("zs", R8A7792_CLK_ZS, CLK_PLL1, 6, 1),
62 DEF_FIXED("hp", R8A7792_CLK_HP, CLK_PLL1, 12, 1),
63 DEF_FIXED("i", R8A7792_CLK_I, CLK_PLL1, 3, 1),
64 DEF_FIXED("b", R8A7792_CLK_B, CLK_PLL1, 12, 1),
65 DEF_FIXED("p", R8A7792_CLK_P, CLK_PLL1, 24, 1),
66 DEF_FIXED("cl", R8A7792_CLK_CL, CLK_PLL1, 48, 1),
[all …]
Dr8a7795-cpg-mssr.c65 DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
66 DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4, CLK_PLL1_DIV2, 2, 1),
67 DEF_FIXED(".s0", CLK_S0, CLK_PLL1_DIV2, 2, 1),
68 DEF_FIXED(".s1", CLK_S1, CLK_PLL1_DIV2, 3, 1),
69 DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1),
70 DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1),
71 DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1),
72 DEF_FIXED(".rpcsrc", CLK_RPCSRC, CLK_PLL1, 2, 1),
75 DEF_FIXED("ztr", R8A7795_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
76 DEF_FIXED("ztrd2", R8A7795_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
[all …]
Dr8a77970-cpg-mssr.c68 DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
69 DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4, CLK_PLL1_DIV2, 2, 1),
70 DEF_FIXED(".s1", CLK_S1, CLK_PLL1_DIV2, 4, 1),
71 DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 6, 1),
72 DEF_FIXED(".rpcsrc", CLK_RPCSRC, CLK_PLL1, 2, 1),
76 DEF_FIXED("ztr", R8A77970_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
77 DEF_FIXED("ztrd2", R8A77970_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
78 DEF_FIXED("zt", R8A77970_CLK_ZT, CLK_PLL1_DIV2, 4, 1),
79 DEF_FIXED("zx", R8A77970_CLK_ZX, CLK_PLL1_DIV2, 3, 1),
80 DEF_FIXED("s1d1", R8A77970_CLK_S1D1, CLK_S1, 1, 1),
[all …]
Dr8a7794-cpg-mssr.c54 DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
64 DEF_FIXED("z2", R8A7794_CLK_Z2, CLK_PLL0, 1, 1),
65 DEF_FIXED("zg", R8A7794_CLK_ZG, CLK_PLL1, 6, 1),
66 DEF_FIXED("zx", R8A7794_CLK_ZX, CLK_PLL1, 3, 1),
67 DEF_FIXED("zs", R8A7794_CLK_ZS, CLK_PLL1, 6, 1),
68 DEF_FIXED("hp", R8A7794_CLK_HP, CLK_PLL1, 12, 1),
69 DEF_FIXED("i", R8A7794_CLK_I, CLK_PLL1, 2, 1),
70 DEF_FIXED("b", R8A7794_CLK_B, CLK_PLL1, 12, 1),
71 DEF_FIXED("p", R8A7794_CLK_P, CLK_PLL1, 24, 1),
72 DEF_FIXED("cl", R8A7794_CLK_CL, CLK_PLL1, 48, 1),
[all …]
Dr8a7790-cpg-mssr.c54 DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
66 DEF_FIXED("z2", R8A7790_CLK_Z2, CLK_PLL1, 2, 1),
67 DEF_FIXED("zg", R8A7790_CLK_ZG, CLK_PLL1, 3, 1),
68 DEF_FIXED("zx", R8A7790_CLK_ZX, CLK_PLL1, 3, 1),
69 DEF_FIXED("zs", R8A7790_CLK_ZS, CLK_PLL1, 6, 1),
70 DEF_FIXED("hp", R8A7790_CLK_HP, CLK_PLL1, 12, 1),
71 DEF_FIXED("i", R8A7790_CLK_I, CLK_PLL1, 2, 1),
72 DEF_FIXED("b", R8A7790_CLK_B, CLK_PLL1, 12, 1),
73 DEF_FIXED("p", R8A7790_CLK_P, CLK_PLL1, 24, 1),
74 DEF_FIXED("cl", R8A7790_CLK_CL, CLK_PLL1, 48, 1),
[all …]
Dr8a7791-cpg-mssr.c53 DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
64 DEF_FIXED("zg", R8A7791_CLK_ZG, CLK_PLL1, 3, 1),
65 DEF_FIXED("zx", R8A7791_CLK_ZX, CLK_PLL1, 3, 1),
66 DEF_FIXED("zs", R8A7791_CLK_ZS, CLK_PLL1, 6, 1),
67 DEF_FIXED("hp", R8A7791_CLK_HP, CLK_PLL1, 12, 1),
68 DEF_FIXED("i", R8A7791_CLK_I, CLK_PLL1, 2, 1),
69 DEF_FIXED("b", R8A7791_CLK_B, CLK_PLL1, 12, 1),
70 DEF_FIXED("p", R8A7791_CLK_P, CLK_PLL1, 24, 1),
71 DEF_FIXED("cl", R8A7791_CLK_CL, CLK_PLL1, 48, 1),
72 DEF_FIXED("m2", R8A7791_CLK_M2, CLK_PLL1, 8, 1),
[all …]
Drenesas-cpg-mssr.h72 #define DEF_FIXED(_name, _id, _parent, _div, _mult) \ macro