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Searched refs:DIV_OP (Results 1 – 8 of 8) sorted by relevance

/external/v8/src/mips64/
Ddisasm-mips64.cc1581 if (instr->SaValue() == DIV_OP) { in DecodeTypeRegisterSPECIAL()
1592 if (instr->SaValue() == DIV_OP) { in DecodeTypeRegisterSPECIAL()
1603 if (instr->SaValue() == DIV_OP) { in DecodeTypeRegisterSPECIAL()
1614 if (instr->SaValue() == DIV_OP) { in DecodeTypeRegisterSPECIAL()
Dconstants-mips64.h558 DIV_OP = ((0U << 3) + 2), enumerator
Dassembler-mips64.cc1986 GenInstrRegister(SPECIAL, rs, rt, rd, DIV_OP, DIV_MOD); in div()
2003 GenInstrRegister(SPECIAL, rs, rt, rd, DIV_OP, DIV_MOD_U); in divu()
2040 GenInstrRegister(SPECIAL, rs, rt, rd, DIV_OP, D_DIV_MOD); in ddiv()
2057 GenInstrRegister(SPECIAL, rs, rt, rd, DIV_OP, D_DIV_MOD_U); in ddivu()
Dsimulator-mips64.cc3922 case DIV_OP: in DecodeTypeRegisterSPECIAL()
3952 case DIV_OP: in DecodeTypeRegisterSPECIAL()
3981 case DIV_OP: in DecodeTypeRegisterSPECIAL()
/external/v8/src/mips/
Ddisasm-mips.cc1377 if (instr->SaValue() == DIV_OP) { in DecodeTypeRegisterSPECIAL()
1388 if (instr->SaValue() == DIV_OP) { in DecodeTypeRegisterSPECIAL()
Dconstants-mips.h553 DIV_OP = ((0U << 3) + 2), enumerator
Dassembler-mips.cc1975 GenInstrRegister(SPECIAL, rs, rt, rd, DIV_OP, DIV_MOD); in div()
1986 GenInstrRegister(SPECIAL, rs, rt, rd, DIV_OP, DIV_MOD_U); in divu()
Dsimulator-mips.cc3925 case DIV_OP: in DecodeTypeRegisterSPECIAL()
3960 case DIV_OP: in DecodeTypeRegisterSPECIAL()