| /external/swiftshader/third_party/LLVM/test/MC/Disassembler/ARM/ |
| D | invalid-UQADD8-arm.txt | 9 # DPFrm with bad reg specifier(s)
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| /external/llvm/test/MC/Disassembler/ARM/ |
| D | unpredictable-UQADD8-arm.txt | 9 # DPFrm with bad reg specifier(s)
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/ARM/ |
| D | unpredictable-UQADD8-arm.txt | 9 # DPFrm with bad reg specifier(s)
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/MCTargetDesc/ |
| D | ARMBaseInfo.h | 314 DPFrm = 4 << FormShift, enumerator
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| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| D | ARMBaseInfo.h | 352 DPFrm = 4 << FormShift, enumerator
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| /external/swiftshader/third_party/LLVM/lib/Target/ARM/MCTargetDesc/ |
| D | ARMBaseInfo.h | 335 DPFrm = 4 << FormShift, enumerator
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| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMInstrInfo.td | 870 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
882 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
962 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
974 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
1052 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
1056 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
1092 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
1095 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
1117 def ri : AI1<opcod, (outs), (ins GPR:$Rn, so_imm:$imm), DPFrm, iii,
1128 def rr : AI1<opcod, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, iir,
[all …]
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| D | ARMCodeEmitter.cpp | 548 case ARMII::DPFrm: in emitInstruction()
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| D | ARMInstrFormats.td | 27 def DPFrm : Format<4>;
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | ARMInstrInfo.td | 1361 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm), DPFrm,
1374 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
1434 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm), DPFrm,
1447 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
1566 def ri : AI1<opcod, (outs), (ins GPR:$Rn, mod_imm:$imm), DPFrm, iii,
1580 def rr : AI1<opcod, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, iir,
1698 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
1711 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
1768 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
1781 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
[all …]
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| D | ARMInstrFormats.td | 27 def DPFrm : Format<4>;
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| /external/llvm/lib/Target/ARM/ |
| D | ARMInstrInfo.td | 1257 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm), DPFrm,
1270 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
1330 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm), DPFrm,
1343 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
1462 def ri : AI1<opcod, (outs), (ins GPR:$Rn, mod_imm:$imm), DPFrm, iii,
1476 def rr : AI1<opcod, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, iir,
1594 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
1607 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
1664 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
1677 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
[all …]
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| D | ARMInstrFormats.td | 27 def DPFrm : Format<4>;
|