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Searched refs:DRAMTMG5_TCKE (Results 1 – 4 of 4) sorted by relevance

/external/u-boot/arch/arm/mach-sunxi/dram_timings/
Dlpddr3_stock.c66 DRAMTMG5_TCKESR(tckesr) | DRAMTMG5_TCKE(tcke), in mctl_set_timing_params()
Dddr2_v3s.c67 DRAMTMG5_TCKESR(tckesr) | DRAMTMG5_TCKE(tcke), in mctl_set_timing_params()
Dddr3_1333.c70 DRAMTMG5_TCKESR(tckesr) | DRAMTMG5_TCKE(tcke), in mctl_set_timing_params()
/external/u-boot/arch/arm/include/asm/arch-sunxi/
Ddram_sunxi_dw.h180 #define DRAMTMG5_TCKE(x) ((x) << 0) macro