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Searched refs:DW_OP_reg1 (Results 1 – 22 of 22) sorted by relevance

/external/swiftshader/third_party/llvm-7.0/llvm/test/DebugInfo/X86/
Ddwarfdump-debug-loc-simple.test7 CHECK-NEXT: [0x00000000, 0x00000023): DW_OP_reg1 ECX
18 CHECK-NEXT: [0x00000000, 0x00000023): DW_OP_reg1 ECX
/external/elfutils/backends/
Darm_retval.c44 { .atom = DW_OP_reg1 }, { .atom = DW_OP_piece, .number = 4 },
Dsh_retval.c49 { .atom = DW_OP_reg1 }, { .atom = DW_OP_piece, .number = 4 },
Dm68k_retval.c44 { .atom = DW_OP_reg1 }, { .atom = DW_OP_piece, .number = 4 },
Dx86_64_retval.c44 { .atom = DW_OP_reg1 }, { .atom = DW_OP_piece, .number = 8 },
Daarch64_retval.c198 { .atom = DW_OP_reg1 }, { .atom = DW_OP_piece, .number = 8 } in pass_in_gpr()
/external/libunwind_llvm/src/
Ddwarf2.h159 DW_OP_reg1 = 0x51, // Contents of reg1 enumerator
DDwarfInstructions.hpp648 case DW_OP_reg1: in evaluateExpression()
/external/swiftshader/third_party/llvm-7.0/llvm/test/DebugInfo/Mips/
Ddsr-fixed-objects.ll27 ; CHECK-NEXT: [0x00000028, 0x0000002c): DW_OP_reg1 AT_64
58 ; CHECK-NEXT: [0x00000080, 0x00000084): DW_OP_reg1 AT_64
/external/llvm/test/DebugInfo/Mips/
Ddsr-fixed-objects.ll30 ; x -> DW_OP_reg1(51)
66 ; x -> DW_OP_reg1(51)
/external/swiftshader/third_party/llvm-7.0/llvm/test/DebugInfo/MIR/X86/
Dbit-piece-dh.mir4 # CHECK-NEXT: DW_AT_location {{.*}} (DW_OP_reg1 RDX, DW_OP_bit_piece 0x8 0x8)
/external/swiftshader/third_party/llvm-7.0/llvm/test/DebugInfo/ARM/
DPR16736.ll11 ; DWARF-NEXT: DW_OP_reg1 R1
/external/google-breakpad/src/common/dwarf/
Ddwarf2enums.h413 DW_OP_reg1 =0x51, enumerator
/external/libunwind/include/
Ddwarf.h110 DW_OP_reg1, DW_OP_reg2, DW_OP_reg3, DW_OP_reg4, DW_OP_reg5, enumerator
/external/swiftshader/third_party/LLVM/lib/Support/
DDwarf.cpp365 case DW_OP_reg1: return "DW_OP_reg1"; in OperationEncodingString()
/external/swiftshader/third_party/LLVM/include/llvm/Support/
DDwarf.h376 DW_OP_reg1 = 0x51, enumerator
/external/swiftshader/third_party/llvm-7.0/llvm/test/DebugInfo/AArch64/
Dinlined-argument.ll4 ; CHECK-NEXT: DW_AT_location (DW_OP_reg1 W1)
/external/elfutils/libdw/
Ddwarf.h501 DW_OP_reg1 = 0x51, /* Register 1. */ enumerator
Dknown-dwarf.h499 DWARF_ONE_KNOWN_DW_OP (reg1, DW_OP_reg1) \
/external/swiftshader/third_party/llvm-7.0/llvm/test/DebugInfo/MIR/AArch64/
Dclobber-sp.mir7 # CHECK-NEXT: [0x0000000000000000, 0x0000000000000014): DW_OP_reg1 W1
/external/libunwind/src/dwarf/
DGexpr.c310 case DW_OP_reg0: case DW_OP_reg1: case DW_OP_reg2: in dwarf_eval_expr()
/external/v8/src/
Dgdb-jit.cc1079 DW_OP_reg1 = 0x51, enumerator