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Searched refs:DXnGCR0 (Results 1 – 4 of 4) sorted by relevance

/external/u-boot/arch/arm/mach-sunxi/
Ddram_sun8i_a33.c217 setbits_le32(DXnGCR0(0), 0x3 << 9); in mctl_channel_init()
218 setbits_le32(DXnGCR0(1), 0x3 << 9); in mctl_channel_init()
220 clrbits_le32(DXnGCR0(0), 0x3 << 9); in mctl_channel_init()
221 clrbits_le32(DXnGCR0(1), 0x3 << 9); in mctl_channel_init()
274 writel(0x0, DXnGCR0(1)); /* Disable high DQ */ in mctl_channel_init()
Ddram_sun8i_a83t.c366 writel(0x0, DXnGCR0(1)); /* Disable high DQ */ in mctl_channel_init()
/external/u-boot/arch/arm/include/asm/arch-sunxi/
Ddram_sun8i_a33.h146 #define DXnGCR0(x) (SUNXI_DRAM_CTL0_BASE + 0x00000344 + 0x80 * x) macro
Ddram_sun8i_a83t.h151 #define DXnGCR0(x) (SUNXI_DRAM_CTL0_BASE + 0x00000344 + 0x80 * x) macro