/external/llvm/lib/Target/ARM/ |
D | ARMBaseInstrInfo.cpp | 1081 AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI); in loadRegFromStackSlot() 1082 AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI); in loadRegFromStackSlot() 1091 MIB = AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI); in loadRegFromStackSlot() 1092 MIB = AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI); in loadRegFromStackSlot() 1125 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI); in loadRegFromStackSlot() 1126 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI); in loadRegFromStackSlot() 1127 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI); in loadRegFromStackSlot() 1145 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI); in loadRegFromStackSlot() 1146 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI); in loadRegFromStackSlot() 1147 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI); in loadRegFromStackSlot() [all …]
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D | Thumb2InstrInfo.cpp | 199 AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI); in loadRegFromStackSlot() 200 AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
D | ARMBaseInstrInfo.cpp | 1232 AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI); in loadRegFromStackSlot() 1233 AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI); in loadRegFromStackSlot() 1243 MIB = AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI); in loadRegFromStackSlot() 1244 MIB = AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI); in loadRegFromStackSlot() 1282 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI); in loadRegFromStackSlot() 1283 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI); in loadRegFromStackSlot() 1284 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI); in loadRegFromStackSlot() 1304 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI); in loadRegFromStackSlot() 1305 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI); in loadRegFromStackSlot() 1306 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI); in loadRegFromStackSlot() [all …]
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D | Thumb2InstrInfo.cpp | 215 AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI); in loadRegFromStackSlot() 216 AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
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/external/llvm/include/llvm/CodeGen/ |
D | MachineInstrBuilder.h | 41 DefineNoRead = Define | Undef, enumerator
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/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/ |
D | MachineInstrBuilder.h | 54 DefineNoRead = Define | Undef, enumerator
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
D | X86InstructionSelector.cpp | 1156 .addReg(DstReg, RegState::DefineNoRead, SubIdx) in emitInsertSubreg()
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