Searched refs:DivRemResultReg (Results 1 – 2 of 2) sorted by relevance
1797 unsigned DivRemResultReg; // Register containing the desired result. in X86SelectDivRem() member1909 OpEntry.DivRemResultReg == X86::AH && Subtarget->is64Bit()) { in X86SelectDivRem()1927 .addReg(OpEntry.DivRemResultReg); in X86SelectDivRem()
1891 unsigned DivRemResultReg; // Register containing the desired result. in X86SelectDivRem() member2003 OpEntry.DivRemResultReg == X86::AH && Subtarget->is64Bit()) { in X86SelectDivRem()2021 .addReg(OpEntry.DivRemResultReg); in X86SelectDivRem()