| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUInstructionSelector.cpp | 128 unsigned DstHi = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass); in selectG_ADD() local
145 BuildMI(*BB, &I, DL, TII.get(AMDGPU::S_ADDC_U32), DstHi) in selectG_ADD()
152 .addReg(DstHi) in selectG_ADD()
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| D | SIInstrInfo.cpp | 1196 unsigned DstHi = RI.getSubReg(Dst, AMDGPU::sub1); in expandPostRAPseudo() local
1206 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstHi) in expandPostRAPseudo()
1214 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstHi) in expandPostRAPseudo()
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| D | SIISelLowering.cpp | 3389 unsigned DstHi = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); in EmitInstrWithCustomInserter() local
3398 BuildMI(*BB, MI, DL, TII->get(AMDGPU::V_CNDMASK_B32_e64), DstHi) in EmitInstrWithCustomInserter()
3406 .addReg(DstHi) in EmitInstrWithCustomInserter()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsSEInstrInfo.cpp | 575 unsigned DstHi = getRegisterInfo().getSubReg(DstReg, Mips::sub_hi); in expandPseudoMTLoHi() local
577 HiInst.addReg(DstHi, RegState::Define); in expandPseudoMTLoHi()
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| D | MipsSEFrameLowering.cpp | 249 unsigned DstHi = RegInfo.getSubReg(Dst, Mips::sub_hi); in expandCopyACC() local
256 BuildMI(MBB, I, DL, TII.get(TargetOpcode::COPY), DstHi) in expandCopyACC()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
| D | MipsSEFrameLowering.cpp | 270 unsigned DstHi = RegInfo.getSubReg(Dst, Mips::sub_hi); in expandCopyACC() local
277 BuildMI(MBB, I, DL, TII.get(TargetOpcode::COPY), DstHi) in expandCopyACC()
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| D | MipsSEInstrInfo.cpp | 733 unsigned DstHi = getRegisterInfo().getSubReg(DstReg, Mips::sub_hi); in expandPseudoMTLoHi() local
735 HiInst.addReg(DstHi, RegState::Define); in expandPseudoMTLoHi()
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| /external/llvm/lib/Target/AMDGPU/ |
| D | SIInstrInfo.cpp | 859 unsigned DstHi = RI.getSubReg(Dst, AMDGPU::sub1); in expandPostRAPseudo() local
869 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstHi) in expandPostRAPseudo()
877 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstHi) in expandPostRAPseudo()
888 unsigned DstHi = RI.getSubReg(Dst, AMDGPU::sub1); in expandPostRAPseudo() local
898 BuildMI(MBB, MI, DL, get(AMDGPU::V_CNDMASK_B32_e64), DstHi) in expandPostRAPseudo()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/ |
| D | HexagonFrameLowering.cpp | 1767 unsigned DstHi = HRI.getSubReg(DstR, Hexagon::vsub_hi); in expandLoadVec2() local
1787 BuildMI(B, It, DL, HII.get(LoadOpc), DstHi) in expandLoadVec2()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonFrameLowering.cpp | 1604 unsigned DstHi = HRI.getSubReg(DstR, Hexagon::subreg_hireg); in expandLoadVec2() local
1635 BuildMI(B, It, DL, HII.get(LoadOpc), DstHi) in expandLoadVec2()
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| D | HexagonInstrInfo.cpp | 847 unsigned DstHi = HRI.getSubReg(DestReg, Hexagon::subreg_hireg); in copyPhysReg() local
848 BuildMI(MBB, I, DL, get(Hexagon::V6_pred_and), DstHi) in copyPhysReg()
|