| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUInstructionSelector.cpp | 127 unsigned DstLo = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass); in selectG_ADD() local
138 BuildMI(*BB, &I, DL, TII.get(AMDGPU::S_ADD_U32), DstLo) in selectG_ADD()
150 .addReg(DstLo) in selectG_ADD()
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| D | SIInstrInfo.cpp | 1195 unsigned DstLo = RI.getSubReg(Dst, AMDGPU::sub0); in expandPostRAPseudo() local
1203 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstLo) in expandPostRAPseudo()
1211 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstLo) in expandPostRAPseudo()
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| D | SIISelLowering.cpp | 3388 unsigned DstLo = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); in EmitInstrWithCustomInserter() local
3394 BuildMI(*BB, MI, DL, TII->get(AMDGPU::V_CNDMASK_B32_e64), DstLo) in EmitInstrWithCustomInserter()
3404 .addReg(DstLo) in EmitInstrWithCustomInserter()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsSEInstrInfo.cpp | 574 unsigned DstLo = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo); in expandPseudoMTLoHi() local
576 LoInst.addReg(DstLo, RegState::Define); in expandPseudoMTLoHi()
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| D | MipsSEFrameLowering.cpp | 248 unsigned DstLo = RegInfo.getSubReg(Dst, Mips::sub_lo); in expandCopyACC() local
253 BuildMI(MBB, I, DL, TII.get(TargetOpcode::COPY), DstLo) in expandCopyACC()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
| D | MipsSEFrameLowering.cpp | 269 unsigned DstLo = RegInfo.getSubReg(Dst, Mips::sub_lo); in expandCopyACC() local
274 BuildMI(MBB, I, DL, TII.get(TargetOpcode::COPY), DstLo) in expandCopyACC()
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| D | MipsSEInstrInfo.cpp | 732 unsigned DstLo = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo); in expandPseudoMTLoHi() local
734 LoInst.addReg(DstLo, RegState::Define); in expandPseudoMTLoHi()
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| /external/llvm/lib/Target/AMDGPU/ |
| D | SIInstrInfo.cpp | 858 unsigned DstLo = RI.getSubReg(Dst, AMDGPU::sub0); in expandPostRAPseudo() local
866 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstLo) in expandPostRAPseudo()
874 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstLo) in expandPostRAPseudo()
887 unsigned DstLo = RI.getSubReg(Dst, AMDGPU::sub0); in expandPostRAPseudo() local
893 BuildMI(MBB, MI, DL, get(AMDGPU::V_CNDMASK_B32_e64), DstLo) in expandPostRAPseudo()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/ |
| D | HexagonFrameLowering.cpp | 1768 unsigned DstLo = HRI.getSubReg(DstR, Hexagon::vsub_lo); in expandLoadVec2() local
1779 BuildMI(B, It, DL, HII.get(LoadOpc), DstLo) in expandLoadVec2()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonFrameLowering.cpp | 1605 unsigned DstLo = HRI.getSubReg(DstR, Hexagon::subreg_loreg); in expandLoadVec2() local
1624 BuildMI(B, It, DL, HII.get(LoadOpc), DstLo) in expandLoadVec2()
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| D | HexagonInstrInfo.cpp | 850 unsigned DstLo = HRI.getSubReg(DestReg, Hexagon::subreg_loreg); in copyPhysReg() local
851 BuildMI(MBB, I, DL, get(Hexagon::V6_pred_and), DstLo) in copyPhysReg()
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