Searched refs:EPLL (Results 1 – 5 of 5) sorted by relevance
140 if (pllreg == EPLL || pllreg == RPLL) { in exynos_get_pll_clk()198 case EPLL: in exynos4_get_pll_clk()228 case EPLL: in exynos4x12_get_pll_clk()259 case EPLL: in exynos5_get_pll_clk()317 case EPLL: in exynos542x_get_pll_clk()440 sclk = exynos5_get_pll_clk(EPLL); in exynos5_get_periph_rate()534 sclk = exynos542x_get_pll_clk(EPLL); in exynos542x_get_periph_rate()654 sclk = get_pll_clk(EPLL); in exynos4_get_pwm_clk()715 sclk = get_pll_clk(EPLL); in exynos4_get_uart_clk()761 sclk = get_pll_clk(EPLL); in exynos4x12_get_uart_clk()[all …]
39 case EPLL: in s5pc100_get_pll_clk()90 case EPLL: in s5pc110_get_pll_clk()
13 #define EPLL 2 macro
12 #define EPLL 2 macro
55 samsung,pclk-name: parent clock identifier: 1(MPLL), 2(EPLL), 3(VPLL)