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Searched refs:FFBH (Results 1 – 5 of 5) sorted by relevance

/external/llvm/test/CodeGen/AMDGPU/
Dctlz.ll101 ; SI-DAG: v_ffbh_u32_e32 [[FFBH:v[0-9]+]], [[VAL]]
103 ; SI-DAG: v_cndmask_b32_e64 [[CORRECTED_FFBH:v[0-9]+]], [[FFBH]], 32, vcc
233 ; SI: v_ffbh_u32_e32 [[FFBH:v[0-9]+]], [[VAL]]
234 ; SI: buffer_store_byte [[FFBH]],
246 ; SI: v_ffbh_u32_e32 [[FFBH:v[0-9]+]], [[VAL]]
247 ; SI: buffer_store_short [[FFBH]],
259 ; SI: v_ffbh_u32_e32 [[FFBH:v[0-9]+]], [[VAL]]
260 ; SI: v_and_b32_e32 [[TRUNC:v[0-9]+]], 0x7f, [[FFBH]]
Dctlz_zero_undef.ll83 ; SI: v_ffbh_u32_e32 [[FFBH:v[0-9]+]], [[VAL]]
84 ; SI: v_add_i32_e32 [[RESULT:v[0-9]+]], vcc, 0xffffffe8, [[FFBH]]
177 ; SI: v_ffbh_u32_e32 [[FFBH:v[0-9]+]], [[VAL]]
178 ; SI: buffer_store_byte [[FFBH]],
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/
Dctlz.ll107 ; SI-DAG: v_ffbh_u32_e32 [[FFBH:v[0-9]+]], [[VAL]]
108 ; VI-DAG: v_ffbh_u32_sdwa [[FFBH:v[0-9]+]], [[VAL]] dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WO…
112 ; GCN: v_cndmask_b32_e32 [[SELECT:v[0-9]+]], 32, [[FFBH]], vcc
252 ; GCN: v_ffbh_u32_e32 [[FFBH:v[0-9]+]], [[VAL]]
253 ; GCN: {{buffer|flat}}_store_byte [[FFBH]],
267 ; SI: v_ffbh_u32_e32 [[FFBH:v[0-9]+]], [[VAL]]
268 ; SI: buffer_store_short [[FFBH]],
281 ; GCN: v_ffbh_u32_e32 [[FFBH:v[0-9]+]], [[VAL]]
282 ; GCN: v_and_b32_e32 [[TRUNC:v[0-9]+]], 0x7f, [[FFBH]]
Dctlz_zero_undef.ll187 ; GCN: v_ffbh_u32_e32 [[FFBH:v[0-9]+]], [[VAL]]
188 ; GCN: {{buffer|flat}}_store_byte [[FFBH]],
/external/llvm/lib/Target/AMDGPU/
DAMDGPUISelLowering.cpp2491 SDValue FFBH = DAG.getNode(AMDGPUISD::FFBH_U32, SL, MVT::i32, Op); in getFFBH_U32() local
2493 FFBH = DAG.getNode(ISD::TRUNCATE, SL, VT, FFBH); in getFFBH_U32()
2495 return FFBH; in getFFBH_U32()