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Searched refs:FRAC_PLL_INT_DIV_CTL_VAL (Results 1 – 2 of 2) sorted by relevance

/external/u-boot/arch/arm/mach-imx/mx8m/
Dclock.c577 val_cfg1 = FRAC_PLL_INT_DIV_CTL_VAL(49); in frac_pll_init()
579 val_cfg1 = FRAC_PLL_INT_DIV_CTL_VAL(79); in frac_pll_init()
/external/u-boot/arch/arm/include/asm/arch-mx8m/
Dclock.h529 #define FRAC_PLL_INT_DIV_CTL_VAL(n) ((n) & 0x7f) macro