| /external/virglrenderer/tests/ |
| D | large_shader.h | 65 33: FRC TEMP[13].xyz, TEMP[11].xyzz
74 42: FRC TEMP[22].x, TEMP[21].xxxx
78 46: FRC TEMP[26].x, TEMP[25].xxxx
83 51: FRC TEMP[31].x, TEMP[30].xxxx
87 55: FRC TEMP[35].x, TEMP[34].xxxx
93 61: FRC TEMP[41].x, TEMP[40].xxxx
97 65: FRC TEMP[45].x, TEMP[44].xxxx
102 70: FRC TEMP[50].x, TEMP[49].xxxx
106 74: FRC TEMP[54].x, TEMP[53].xxxx
116 84: FRC TEMP[63].xyz, TEMP[11].xyzz
[all …]
|
| /external/llvm/lib/Target/PowerPC/ |
| D | PPCInstrQPX.td | 40 : AForm_1<opcode, xo, (outs qfrc:$FRT), (ins qfrc:$FRA, qfrc:$FRB, qfrc:$FRC),
41 !strconcat(opc, " $FRT, $FRA, $FRC, $FRB"), IIC_FPFused,
42 [(set v4f64:$FRT, (IntID v4f64:$FRA, v4f64:$FRB, v4f64:$FRC))]>;
45 : AForm_1<opcode, xo, (outs qfrc:$FRT), (ins qfrc:$FRA, qfrc:$FRB, qfrc:$FRC),
46 !strconcat(opc, " $FRT, $FRA, $FRC, $FRB"), IIC_VecPerm,
47 [(set v4f64:$FRT, (IntID v4f64:$FRA, v4f64:$FRB, v4f64:$FRC))]>;
55 : AForm_3<opcode, xo, (outs qfrc:$FRT), (ins qfrc:$FRA, qfrc:$FRC),
56 !strconcat(opc, " $FRT, $FRA, $FRC"), IIC_FPGeneral,
57 [(set v4f64:$FRT, (IntID v4f64:$FRA, v4f64:$FRC))]>;
156 (outs qfrc:$FRT), (ins qfrc:$FRA, qfrc:$FRC),
[all …]
|
| D | PPCInstrInfo.td | 2532 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2533 "fmadd", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused,
2534 [(set f64:$FRT, (fma f64:$FRA, f64:$FRC, f64:$FRB))]>;
2536 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2537 "fmadds", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2538 [(set f32:$FRT, (fma f32:$FRA, f32:$FRC, f32:$FRB))]>;
2540 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2541 "fmsub", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused,
2543 (fma f64:$FRA, f64:$FRC, (fneg f64:$FRB)))]>;
2545 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/ |
| D | PPCInstrQPX.td | 40 : AForm_1<opcode, xo, (outs qfrc:$FRT), (ins qfrc:$FRA, qfrc:$FRB, qfrc:$FRC),
41 !strconcat(opc, " $FRT, $FRA, $FRC, $FRB"), IIC_FPFused,
42 [(set v4f64:$FRT, (IntID v4f64:$FRA, v4f64:$FRB, v4f64:$FRC))]>;
45 : AForm_1<opcode, xo, (outs qfrc:$FRT), (ins qfrc:$FRA, qfrc:$FRB, qfrc:$FRC),
46 !strconcat(opc, " $FRT, $FRA, $FRC, $FRB"), IIC_VecPerm,
47 [(set v4f64:$FRT, (IntID v4f64:$FRA, v4f64:$FRB, v4f64:$FRC))]>;
55 : AForm_3<opcode, xo, (outs qfrc:$FRT), (ins qfrc:$FRA, qfrc:$FRC),
56 !strconcat(opc, " $FRT, $FRA, $FRC"), IIC_FPGeneral,
57 [(set v4f64:$FRT, (IntID v4f64:$FRA, v4f64:$FRC))]>;
156 (outs qfrc:$FRT), (ins qfrc:$FRA, qfrc:$FRC),
[all …]
|
| D | PPCInstrInfo.td | 2812 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2813 "fmadd", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused,
2814 [(set f64:$FRT, (fma f64:$FRA, f64:$FRC, f64:$FRB))]>;
2816 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2817 "fmadds", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2818 [(set f32:$FRT, (fma f32:$FRA, f32:$FRC, f32:$FRB))]>;
2820 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2821 "fmsub", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused,
2823 (fma f64:$FRA, f64:$FRC, (fneg f64:$FRB)))]>;
2825 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/ |
| D | fract.f64.ll | 12 ; SI-DAG: v_fract_f64_e32 [[FRC:v\[[0-9]+:[0-9]+\]]], v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]]
15 ; SI-DAG: v_min_f64 v{{\[}}[[MINLO:[0-9]+]]:[[MINHI:[0-9]+]]], [[FRC]], v{{\[}}[[UPLO]]:[[UPHI]]]
39 ; SI-DAG: v_fract_f64_e64 [[FRC:v\[[0-9]+:[0-9]+\]]], -v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]]
42 ; SI-DAG: v_min_f64 v{{\[}}[[MINLO:[0-9]+]]:[[MINHI:[0-9]+]]], [[FRC]], v{{\[}}[[UPLO]]:[[UPHI]]]
67 ; SI-DAG: v_fract_f64_e64 [[FRC:v\[[0-9]+:[0-9]+\]]], -|v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]]|
70 ; SI-DAG: v_min_f64 v{{\[}}[[MINLO:[0-9]+]]:[[MINHI:[0-9]+]]], [[FRC]], v{{\[}}[[UPLO]]:[[UPHI]]]
|
| /external/llvm/test/CodeGen/AMDGPU/ |
| D | fract.f64.ll | 12 ; SI-DAG: v_fract_f64_e32 [[FRC:v\[[0-9]+:[0-9]+\]]], v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]]
15 ; SI-DAG: v_min_f64 v{{\[}}[[MINLO:[0-9]+]]:[[MINHI:[0-9]+]]], v{{\[}}[[UPLO]]:[[UPHI]]], [[FRC]]
39 ; SI-DAG: v_fract_f64_e64 [[FRC:v\[[0-9]+:[0-9]+\]]], -v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]]
42 ; SI-DAG: v_min_f64 v{{\[}}[[MINLO:[0-9]+]]:[[MINHI:[0-9]+]]], v{{\[}}[[UPLO]]:[[UPHI]]], [[FRC]]
67 ; SI-DAG: v_fract_f64_e64 [[FRC:v\[[0-9]+:[0-9]+\]]], -|v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]]|
70 ; SI-DAG: v_min_f64 v{{\[}}[[MINLO:[0-9]+]]:[[MINHI:[0-9]+]]], v{{\[}}[[UPLO]]:[[UPHI]]], [[FRC]]
|
| /external/clang/test/Profile/ |
| D | objc-general.m | 34 // PGOGEN: @[[FRC:"__profc_objc_general.m_\+\[A foreach_\]"]] = private global [2 x i64] zeroinitia…
45 // PGOGEN: store {{.*}} @[[FRC]], i64 0, i64 0
49 // PGOGEN: store {{.*}} @[[FRC]], i64 0, i64 1
|
| /external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
| D | PPCInstrInfo.td | 1226 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
1227 "fmadd $FRT, $FRA, $FRC, $FRB", FPFused,
1228 [(set F8RC:$FRT, (fadd (fmul F8RC:$FRA, F8RC:$FRC),
1232 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
1233 "fmadds $FRT, $FRA, $FRC, $FRB", FPGeneral,
1234 [(set F4RC:$FRT, (fadd (fmul F4RC:$FRA, F4RC:$FRC),
1238 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
1239 "fmsub $FRT, $FRA, $FRC, $FRB", FPFused,
1240 [(set F8RC:$FRT, (fsub (fmul F8RC:$FRA, F8RC:$FRC),
1244 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
[all …]
|
| D | PPCInstrFormats.td | 669 bits<5> FRC;
679 let Inst{21-25} = FRC;
687 let FRC = 0;
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
| D | X86InstrAVX512.td | 108 RegisterClass FRC = !if (!eq (EltTypeName, "f32"), FR32X, FR64X);
1123 def : Pat<(DestInfo.VT (X86VBroadcast SrcInfo.FRC:$src)),
1125 (SrcInfo.VT (COPY_TO_REGCLASS SrcInfo.FRC:$src, SrcInfo.RC)))>;
1127 (X86VBroadcast SrcInfo.FRC:$src),
1131 (SrcInfo.VT (COPY_TO_REGCLASS SrcInfo.FRC:$src, SrcInfo.RC)))>;
1133 (X86VBroadcast SrcInfo.FRC:$src),
1136 DestInfo.KRCWM:$mask, (SrcInfo.VT (COPY_TO_REGCLASS SrcInfo.FRC:$src, SrcInfo.RC)))>;
2110 (outs _.KRC:$dst), (ins _.FRC:$src1, _.FRC:$src2, AVXCC:$cc),
2113 [(set _.KRC:$dst, (OpNode _.FRC:$src1,
2114 _.FRC:$src2,
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/ |
| D | HexagonBitSimplify.cpp | 1348 const TargetRegisterClass *FRC = HBS::getFinalVRegClass(RD, MRI); in processBlock() local
1349 unsigned NewR = MRI.createVirtualRegister(FRC); in processBlock()
1544 auto *FRC = HBS::getFinalVRegClass(Inp, MRI); in findMatch() local
1555 if (FRC != MRI.getRegClass(R)) in findMatch()
1610 auto *FRC = HBS::getFinalVRegClass(R, MRI); in processBlock() local
1613 unsigned NewR = MRI.createVirtualRegister(FRC); in processBlock()
1622 if (FRC == &Hexagon::DoubleRegsRegClass || in processBlock()
1623 FRC == &Hexagon::HvxWRRegClass) { in processBlock()
1625 unsigned SubLo = HRI.getHexagonSubRegIndex(*FRC, Hexagon::ps_sub_lo); in processBlock()
1626 unsigned SubHi = HRI.getHexagonSubRegIndex(*FRC, Hexagon::ps_sub_hi); in processBlock()
[all …]
|
| /external/mesa3d/src/gallium/tests/graw/fragment-shader/ |
| D | frag-frc.sh | 11 FRC OUT[0], TEMP[0]
|
| /external/mesa3d/src/gallium/tests/graw/vertex-shader/ |
| D | vert-frc.sh | 13 FRC OUT[1], TEMP[0]
|
| /external/llvm/lib/Target/X86/ |
| D | X86InstrAVX512.td | 123 RegisterClass FRC = !if (!eq (EltTypeName, "f32"), FR32X, FR64X);
803 (ins SrcInfo.FRC:$src), OpcodeStr#"\t{$src, $dst|$dst, $src}",
804 [(set DestInfo.RC:$dst, (DestInfo.VT (X86VBroadcast SrcInfo.FRC:$src)))]>,
809 (ins DestInfo.RC:$src0, DestInfo.KRCWM:$mask, SrcInfo.FRC:$src),
813 (DestInfo.VT (X86VBroadcast SrcInfo.FRC:$src)),
818 (ins DestInfo.KRCWM:$mask, SrcInfo.FRC:$src),
822 (DestInfo.VT (X86VBroadcast SrcInfo.FRC:$src)),
1406 (outs _.KRC:$dst), (ins _.FRC:$src1, _.FRC:$src2, AVXCC:$cc),
1409 [(set _.KRC:$dst, (OpNode _.FRC:$src1,
1410 _.FRC:$src2,
[all …]
|
| /external/mesa3d/src/gallium/auxiliary/tgsi/ |
| D | tgsi_opcode_tmp.h | 59 OP11(FRC)
|
| D | tgsi_info_opcodes.h | 25 OPCODE(1, 1, COMP, FRC)
|
| /external/mesa3d/src/mesa/program/ |
| D | program_lexer.l | 199 FRC{sat} { return_opcode( 1, VECTOR_OP, FRC, 3); }
|
| /external/virglrenderer/src/gallium/auxiliary/tgsi/ |
| D | tgsi_opcode_tmp.h | 80 OP11(FRC)
|
| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonBitSimplify.cpp | 1293 const TargetRegisterClass *FRC = HBS::getFinalVRegClass(RD, MRI); in processBlock() local
1294 unsigned NewR = MRI.createVirtualRegister(FRC); in processBlock()
1554 auto *FRC = HBS::getFinalVRegClass(MR, MRI); in processBlock() local
1555 unsigned NewR = MRI.createVirtualRegister(FRC); in processBlock()
2152 const TargetRegisterClass *FRC = HBS::getFinalVRegClass(RD, MRI); in processBlock() local
2155 if (FRC->getID() == Hexagon::DoubleRegsRegClassID) { in processBlock()
2161 if (FRC->getID() == Hexagon::IntRegsRegClassID) { in processBlock()
2169 if (FRC->getID() == Hexagon::PredRegsRegClassID) { in processBlock()
|
| /external/mesa3d/src/gallium/drivers/etnaviv/ |
| D | etnaviv_disasm.c | 482 OPC(FRC),
|
| /external/mesa3d/src/intel/compiler/ |
| D | brw_vec4.h | 195 EMIT1(FRC)
|
| D | brw_vec4_builder.h | 417 ALU1(FRC) in ALU2_ACC()
|
| D | brw_eu.h | 179 ALU1(FRC)
|
| D | brw_fs_builder.h | 471 ALU1(FRC) in ALU2_ACC()
|