Searched refs:FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT (Results 1 – 15 of 15) sorted by relevance
50 srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; in checkboard()102 srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; in board_mux_lane()
39 srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; in board_eth_init()
38 srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; in board_eth_init()
131 cfg >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; in serdes_get_first_lane()354 FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT, in fsl_serdes_init()
240 srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; in initialize_lane_to_slot()263 srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; in board_eth_init()
96 srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; in board_mux_lane_to_slot()
214 srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; in board_ft_fman_fixup_port()453 srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; in initialize_lane_to_slot()525 srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; in board_eth_init()
100 srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; in brd_mux_lane_to_slot()
49 srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; in board_eth_init()
165 serdes1_prtcl >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; in board_eth_init()
344 serdes1_prtcl >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; in configure_vsc3316_3308()788 serdes1_prtcl >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; in config_serdes1_refclks()
191 >> FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; in initialize_lane_to_slot()
1763 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 26 macro1773 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 25 macro1779 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 24 macro1799 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 23 macro1813 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 24 macro
353 srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; in config_frontside_crossbar_vsc3316()
497 srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; in board_eth_init()