Searched refs:FSL_DDR_CS0_CS1_CS2_CS3 (Results 1 – 5 of 5) sorted by relevance
721 return FSL_DDR_CS0_CS1_CS2_CS3; in auto_bank_intlv()727 return FSL_DDR_CS0_CS1_CS2_CS3; in auto_bank_intlv()731 return FSL_DDR_CS0_CS1_CS2_CS3; in auto_bank_intlv()1206 popts->ba_intlv_ctl = FSL_DDR_CS0_CS1_CS2_CS3; in populate_memctl_options()1212 switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) { in populate_memctl_options()1213 case FSL_DDR_CS0_CS1_CS2_CS3: in populate_memctl_options()
312 FSL_DDR_CS0_CS1_CS2_CS3) { in __step_assign_addresses()313 case FSL_DDR_CS0_CS1_CS2_CS3: in __step_assign_addresses()
306 case FSL_DDR_CS0_CS1_CS2_CS3: in print_ddr_info()
2441 switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) { in compute_fsl_memctl_config_regs()2442 case FSL_DDR_CS0_CS1_CS2_CS3: in compute_fsl_memctl_config_regs()2467 switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) { in compute_fsl_memctl_config_regs()2468 case FSL_DDR_CS0_CS1_CS2_CS3: in compute_fsl_memctl_config_regs()
86 #define FSL_DDR_CS0_CS1_CS2_CS3 (FSL_DDR_CS0_CS1_AND_CS2_CS3 | 0x04) macro