Home
last modified time | relevance | path

Searched refs:GENMASK (Results 1 – 25 of 72) sorted by relevance

123

/external/u-boot/drivers/mtd/nand/
Ddenali.h21 #define LOAD_WAIT_CNT__VALUE GENMASK(15, 0)
24 #define PROGRAM_WAIT_CNT__VALUE GENMASK(15, 0)
27 #define ERASE_WAIT_CNT__VALUE GENMASK(15, 0)
30 #define INT_MON_CYCCNT__VALUE GENMASK(15, 0)
52 #define PREFETCH_MODE__PREFETCH_BURST_LENGTH GENMASK(15, 4)
64 #define TWHR2_AND_WE_2_RE__WE_2_RE GENMASK(5, 0)
65 #define TWHR2_AND_WE_2_RE__TWHR2 GENMASK(13, 8)
69 #define TCWAW_AND_ADDR_2_DATA__ADDR_2_DATA GENMASK(6, 0)
70 #define TCWAW_AND_ADDR_2_DATA__TCWAW GENMASK(13, 8)
73 #define RE_2_WE__VALUE GENMASK(5, 0)
[all …]
/external/u-boot/drivers/pinctrl/rockchip/
Dpinctrl_rk3368.c22 GPIO0B5_MASK = GENMASK(GPIO0B5_SHIFT + 1, GPIO0B5_SHIFT),
27 GPIO0B4_MASK = GENMASK(GPIO0B4_SHIFT + 1, GPIO0B4_SHIFT),
32 GPIO0B3_MASK = GENMASK(GPIO0B3_SHIFT + 1, GPIO0B3_SHIFT),
37 GPIO0B2_MASK = GENMASK(GPIO0B2_SHIFT + 1, GPIO0B2_SHIFT),
45 GPIO0C7_MASK = GENMASK(GPIO0C7_SHIFT + 1, GPIO0C7_SHIFT),
52 GPIO0C6_MASK = GENMASK(GPIO0C6_SHIFT + 1, GPIO0C6_SHIFT),
59 GPIO0C5_MASK = GENMASK(GPIO0C5_SHIFT + 1, GPIO0C5_SHIFT),
66 GPIO0C4_MASK = GENMASK(GPIO0C4_SHIFT + 1, GPIO0C4_SHIFT),
73 GPIO0C3_MASK = GENMASK(GPIO0C3_SHIFT + 1, GPIO0C3_SHIFT),
80 GPIO0C2_MASK = GENMASK(GPIO0C2_SHIFT + 1, GPIO0C2_SHIFT),
[all …]
/external/u-boot/drivers/phy/
Dmeson-gxl-usb3.c24 #define USB_R0_P30_FSEL_MASK GENMASK(5, 0)
28 #define USB_R0_P30_ACJT_LEVEL_MASK GENMASK(13, 9)
29 #define USB_R0_P30_TX_BOOST_LEVEL_MASK GENMASK(16, 14)
32 #define USB_R0_P30_PCS_RX_LOS_MASK_VAL_MASK GENMASK(28, 19)
33 #define USB_R0_U2D_SS_SCALEDOWN_MODE_MASK GENMASK(30, 29)
39 #define USB_R1_U3H_HUB_PORT_OVERCURRENT_MASK GENMASK(6, 2)
40 #define USB_R1_U3H_HUB_PORT_PERM_ATTACH_MASK GENMASK(11, 7)
41 #define USB_R1_U3H_HOST_U2_PORT_DISABLE_MASK GENMASK(15, 12)
45 #define USB_R1_U3H_FLADJ_30MHZ_REG_MASK GENMASK(24, 19)
46 #define USB_R1_P30_PCS_TX_SWING_FULL_MASK GENMASK(31, 25)
[all …]
Dmeson-gxl-usb2.c42 #define U2P_R0_FSEL_MASK GENMASK(19, 17)
43 #define U2P_R0_REF_CLK_SEL_MASK GENMASK(21, 20)
45 #define U2P_R0_V_ATE_TEST_EN_B_MASK GENMASK(24, 23)
61 #define U2P_R1_TX_PREEMP_AMP_TUNE_MASK GENMASK(8, 7)
62 #define U2P_R1_TX_RES_TUNE_MASK GENMASK(10, 9)
63 #define U2P_R1_TX_RISE_TUNE_MASK GENMASK(12, 11)
64 #define U2P_R1_TX_VREF_TUNE_MASK GENMASK(16, 13)
65 #define U2P_R1_TX_FSLS_TUNE_MASK GENMASK(20, 17)
66 #define U2P_R1_TX_HSXV_TUNE_MASK GENMASK(22, 21)
67 #define U2P_R1_OTG_TUNE_MASK GENMASK(25, 23)
[all …]
/external/u-boot/arch/arm/include/asm/arch-rockchip/
Dcru_rk3368.h59 PLL_NR_MASK = GENMASK(13, 8),
61 PLL_OD_MASK = GENMASK(3, 0),
66 PLL_NF_MASK = GENMASK(12, 0),
70 PLL_BWADJ_MASK = GENMASK(11, 0),
74 PLL_MODE_MASK = GENMASK(9, 8),
80 PLL_RESET_MASK = GENMASK(5, 5),
84 MCU_STCLK_DIV_MASK = GENMASK(10, 8),
90 MCU_CLK_DIV_MASK = GENMASK(4, 0),
94 CLK_SARADC_DIV_CON_MASK = GENMASK(15, 8),
99 GMAC_DIV_CON_MASK = GENMASK(4, 0),
[all …]
Dgrf_rk3368.h108 MCU_SRAM_BASE_BIT27_BIT12_MASK = GENMASK(15, 0),
114 MCU_EXSRAM_BASE_BIT27_BIT12_MASK = GENMASK(15, 0),
120 MCU_EXPERI_BASE_BIT27_BIT12_MASK = GENMASK(15, 0),
126 MCU_EXPERI_BASE_BIT31_BIT28_MASK = GENMASK(15, 12),
128 MCU_EXSRAM_BASE_BIT31_BIT28_MASK = GENMASK(11, 8),
130 MCU_SRAM_BASE_BIT31_BIT28_MASK = GENMASK(7, 4),
132 MCU_CODE_BASE_BIT31_BIT28_MASK = GENMASK(3, 0),
/external/u-boot/drivers/adc/
Dmeson-saradc.c22 #define MESON_SAR_ADC_REG0_BUSY_MASK GENMASK(30, 28)
28 #define MESON_SAR_ADC_REG0_FIFO_COUNT_MASK GENMASK(25, 21)
29 #define MESON_SAR_ADC_REG0_ADC_BIAS_CTRL_MASK GENMASK(20, 19)
30 #define MESON_SAR_ADC_REG0_CURR_CHAN_ID_MASK GENMASK(18, 16)
33 #define MESON_SAR_ADC_REG0_CHAN_DELTA_EN_MASK GENMASK(13, 12)
36 #define MESON_SAR_ADC_REG0_FIFO_CNT_IRQ_MASK GENMASK(8, 4)
43 #define MESON_SAR_ADC_CHAN_LIST_MAX_INDEX_MASK GENMASK(26, 24)
45 (GENMASK(2, 0) << ((_chan) * 3))
51 (GENMASK(17, 16) << ((_chan) * 2))
55 (GENMASK(1, 0) << ((_chan) * 2))
[all …]
/external/u-boot/drivers/video/stm32/
Dstm32_ltdc.c71 #define SSCR_VSH GENMASK(10, 0) /* Vertical Synchronization Height */
72 #define SSCR_HSW GENMASK(27, 16) /* Horizontal Synchronization Width */
74 #define BPCR_AVBP GENMASK(10, 0) /* Accumulated Vertical Back Porch */
75 #define BPCR_AHBP GENMASK(27, 16) /* Accumulated Horizontal Back Porch */
77 #define AWCR_AAH GENMASK(10, 0) /* Accumulated Active Height */
78 #define AWCR_AAW GENMASK(27, 16) /* Accumulated Active Width */
80 #define TWCR_TOTALH GENMASK(10, 0) /* TOTAL Height */
81 #define TWCR_TOTALW GENMASK(27, 16) /* TOTAL Width */
90 #define GC1R_WBCH GENMASK(3, 0) /* Width of Blue CHannel output */
91 #define GC1R_WGCH GENMASK(7, 4) /* Width of Green Channel output */
[all …]
/external/u-boot/drivers/ram/stm32mp1/
Dstm32mp1_ddr_regs.h237 #define DDRCTRL_MSTR_DATA_BUS_WIDTH_MASK GENMASK(13, 12)
243 #define DDRCTRL_STAT_OPERATING_MODE_MASK GENMASK(2, 0)
246 #define DDRCTRL_STAT_SELFREF_TYPE_MASK GENMASK(5, 4)
256 #define DDRCTRL_MRCTRL0_MR_ADDR_MASK GENMASK(15, 12)
266 #define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_MASK GENMASK(27, 16)
279 #define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH GENMASK(12, 8)
280 #define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH GENMASK(4, 0)
310 #define DDRPHYC_PIR_INITSTEPS_MASK GENMASK(31, 7)
314 #define DDRPHYC_PGCR_RFSHDT_MASK GENMASK(28, 25)
327 #define DDRPHYC_ZQ0CRN_ZDATA_MASK GENMASK(27, 0)
[all …]
/external/u-boot/arch/arm/include/asm/arch-meson/
Dsd_emmc.h33 #define CFG_BUS_WIDTH_MASK GENMASK(1, 0)
37 #define CFG_BL_LEN_MASK GENMASK(7, 4)
40 #define CFG_RESP_TIMEOUT_MASK GENMASK(11, 8)
42 #define CFG_RC_CC_MASK GENMASK(15, 12)
48 #define STATUS_MASK GENMASK(15, 0)
49 #define STATUS_ERR_MASK GENMASK(12, 0)
50 #define STATUS_RXD_ERR_MASK GENMASK(7, 0)
61 #define CMD_CFG_LENGTH_MASK GENMASK(8, 0)
/external/u-boot/arch/arm/mach-rockchip/rk3368/
Drk3368.c21 #define MCU_SRAM_BASE_BIT31_BIT28 ((MCU_SRAM_BASE & GENMASK(31, 28)) >> 28)
22 #define MCU_SRAM_BASE_BIT27_BIT12 ((MCU_SRAM_BASE & GENMASK(27, 12)) >> 12)
25 #define MCU_EXSRAM_BASE_BIT31_BIT28 ((MCU_EXSRAM_BASE & GENMASK(31, 28)) >> 28)
26 #define MCU_EXSRAM_BASE_BIT27_BIT12 ((MCU_EXSRAM_BASE & GENMASK(27, 12)) >> 12)
29 #define MCU_EXPERI_BASE_BIT31_BIT28 ((MCU_EXPERI_BASE & GENMASK(31, 28)) >> 28)
30 #define MCU_EXPERI_BASE_BIT27_BIT12 ((MCU_EXPERI_BASE & GENMASK(27, 12)) >> 12)
/external/u-boot/drivers/clk/
Dclk_stm32h7.c27 #define RCC_CR_HSIDIV_MASK GENMASK(4, 3)
30 #define RCC_CFGR_SW_MASK GENMASK(2, 0)
42 #define RCC_PLLCKSELR_PLLSRC_MASK GENMASK(1, 0)
45 #define RCC_PLLCKSELR_DIVM1_MASK GENMASK(9, 4)
47 #define RCC_PLL1DIVR_DIVN1_MASK GENMASK(8, 0)
50 #define RCC_PLL1DIVR_DIVP1_MASK GENMASK(15, 9)
53 #define RCC_PLL1DIVR_DIVQ1_MASK GENMASK(22, 16)
56 #define RCC_PLL1DIVR_DIVR1_MASK GENMASK(30, 24)
59 #define RCC_PLL1FRACR_FRACN1_MASK GENMASK(15, 3)
70 #define RCC_D1CFGR_HPRE_MASK GENMASK(3, 0)
[all …]
Dclk_stm32f.c28 #define RCC_PLLCFGR_PLLM_MASK GENMASK(5, 0)
29 #define RCC_PLLCFGR_PLLN_MASK GENMASK(14, 6)
30 #define RCC_PLLCFGR_PLLP_MASK GENMASK(17, 16)
31 #define RCC_PLLCFGR_PLLQ_MASK GENMASK(27, 24)
38 #define RCC_CFGR_AHB_PSC_MASK GENMASK(7, 4)
39 #define RCC_CFGR_APB1_PSC_MASK GENMASK(12, 10)
40 #define RCC_CFGR_APB2_PSC_MASK GENMASK(15, 13)
43 #define RCC_CFGR_SW_MASK GENMASK(1, 0)
49 #define RCC_CFGR_SWS_MASK GENMASK(3, 2)
57 #define RCC_PLLSAICFGR_PLLSAIN_MASK GENMASK(14, 6)
[all …]
Dclk_stm32mp1.c108 #define RCC_SELR_SRC_MASK GENMASK(2, 0)
134 #define RCC_DIVR_DIV_MASK GENMASK(5, 0)
138 #define RCC_APBXDIV_MASK GENMASK(2, 0)
139 #define RCC_MPUDIV_MASK GENMASK(2, 0)
140 #define RCC_AXIDIV_MASK GENMASK(2, 0)
141 #define RCC_MCUDIV_MASK GENMASK(3, 0)
150 #define RCC_BDCR_LSEDRV_MASK GENMASK(5, 4)
154 #define RCC_BDCR_RTCSRC_MASK GENMASK(17, 16)
171 #define RCC_PLLNCFGR1_DIVM_MASK GENMASK(21, 16)
173 #define RCC_PLLNCFGR1_DIVN_MASK GENMASK(8, 0)
[all …]
/external/u-boot/drivers/net/
Dgmac_rockchip.c76 RK3228_GMAC_CLK_SEL_MASK = GENMASK(9, 8), in rk3228_gmac_fix_mac_speed()
135 RK3328_GMAC_CLK_SEL_MASK = GENMASK(12, 11), in rk3328_gmac_fix_mac_speed()
170 RK3368_GMAC_CLK_SEL_MASK = GENMASK(5, 4), in rk3368_gmac_fix_mac_speed()
263 RK3228_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), in rk3228_gmac_set_to_rgmii()
276 RK3228_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(13, 7), in rk3228_gmac_set_to_rgmii()
279 RK3228_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0), in rk3228_gmac_set_to_rgmii()
327 RK3328_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), in rk3328_gmac_set_to_rgmii()
340 RK3328_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(13, 7), in rk3328_gmac_set_to_rgmii()
343 RK3328_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0), in rk3328_gmac_set_to_rgmii()
368 RK3368_GMAC_PHY_INTF_SEL_MASK = GENMASK(11, 9), in rk3368_gmac_set_to_rgmii()
[all …]
/external/u-boot/drivers/spi/
Dxilinx_spi.c54 #define SPIDTR_8BIT_MASK GENMASK(7, 0)
55 #define SPIDTR_16BIT_MASK GENMASK(15, 0)
56 #define SPIDTR_32BIT_MASK GENMASK(31, 0)
59 #define SPIDRR_8BIT_MASK GENMASK(7, 0)
60 #define SPIDRR_16BIT_MASK GENMASK(15, 0)
61 #define SPIDRR_32BIT_MASK GENMASK(31, 0)
77 #define CONFIG_XILINX_SPI_IDLE_VAL GENMASK(7, 0)
Dtegra210_qspi.c22 #define QSPI_CMD1_MODE_MASK GENMASK(1,0)
24 #define QSPI_CMD1_CS_SEL_MASK GENMASK(1,0)
29 #define QSPI_CMD1_IDLE_SDA_MASK GENMASK(1,0)
39 #define QSPI_CMD1_BITLEN_MASK GENMASK(4,0)
44 #define QSPI_CMD2_TX_CLK_TAP_DELAY_MASK GENMASK(11,6)
46 #define QSPI_CMD2_RX_CLK_TAP_DELAY_MASK GENMASK(5,0)
Dtegra114_spi.c19 #define SPI_CMD1_MODE_MASK GENMASK(1, 0)
21 #define SPI_CMD1_CS_SEL_MASK GENMASK(1, 0)
29 #define SPI_CMD1_IDLE_SDA_MASK GENMASK(1, 0)
39 #define SPI_CMD1_BIT_LEN_MASK GENMASK(4, 0)
44 #define SPI_CMD2_TX_CLK_TAP_DELAY_MASK GENMASK(11, 6)
46 #define SPI_CMD2_RX_CLK_TAP_DELAY_MASK GENMASK(5, 0)
/external/u-boot/arch/arm/mach-stm32mp/
Dcpu.c22 #define RCC_BDCR_RTCSRC GENMASK(17, 16)
42 #define DBGMCU_IDC_DEV_ID_MASK GENMASK(11, 0)
44 #define DBGMCU_IDC_REV_ID_MASK GENMASK(31, 16)
52 #define BOOTROM_MODE_MASK GENMASK(15, 0)
54 #define BOOTROM_INSTANCE_MASK GENMASK(31, 16)
83 writel(GENMASK(25, 0), ETZPC_DECPROT0); in security_init()
/external/u-boot/arch/arm/mach-rockchip/
Drk3368-board-tpl.c49 const u16 SGRF_SOC_CON_SEC = GENMASK(15, 0); in sgrf_init()
51 const u16 SGRF_BUSDMAC_CON1_SEC = GENMASK(15, 12); in sgrf_init()
93 GPIO2D1_MASK = GENMASK(3, 2), in board_debug_uart_init()
97 GPIO2D0_MASK = GENMASK(1, 0), in board_debug_uart_init()
/external/u-boot/arch/arm/mach-stm32mp/include/mach/
Dstm32.h94 #define TAMP_BOOT_MODE_MASK GENMASK(15, 8)
96 #define TAMP_BOOT_DEVICE_MASK GENMASK(7, 4)
97 #define TAMP_BOOT_INSTANCE_MASK GENMASK(3, 0)
/external/u-boot/include/power/
Dstpmu1.h21 #define STPMU1_BUCK_OUTPUT_MASK GENMASK(7, 2)
30 #define STPMU1_LDO12356_OUTPUT_MASK GENMASK(6, 2)
38 #define STPMU1_USB_PWR_SW_EN GENMASK(2, 1)
/external/u-boot/drivers/mmc/
Dstm32_sdmmc2.c59 #define SDMMC_POWER_PWRCTRL GENMASK(1, 0)
65 #define SDMMC_CLKCR_CLKDIV GENMASK(9, 0)
74 #define SDMMC_CLKCR_SELCLKRX_MASK GENMASK(21, 20)
80 #define SDMMC_CMD_CMDINDEX GENMASK(5, 0)
83 #define SDMMC_CMD_WAITRESP GENMASK(9, 8)
97 #define SDMMC_DCTRL_DTMODE GENMASK(3, 2)
98 #define SDMMC_DCTRL_DBLOCKSIZE GENMASK(7, 4)
159 #define SDMMC_ICR_STATIC_FLAGS ((GENMASK(28, 21)) | (GENMASK(11, 0)))
Dsdhci-cadence.c22 #define SDHCI_CDNS_HRS04_RDATA GENMASK(23, 16)
23 #define SDHCI_CDNS_HRS04_WDATA GENMASK(15, 8)
24 #define SDHCI_CDNS_HRS04_ADDR GENMASK(5, 0)
28 #define SDHCI_CDNS_HRS06_TUNE GENMASK(13, 8)
29 #define SDHCI_CDNS_HRS06_MODE GENMASK(2, 0)
/external/u-boot/arch/arm/mach-at91/include/mach/
Datmel_pio4.h34 #define ATMEL_PIO_CFGR_FUNC_MASK GENMASK(2, 0)
50 #define ATMEL_PIO_DRVSTR_MASK GENMASK(17, 16)
54 #define ATMEL_PIO_CFGR_EVTSEL_MASK GENMASK(26, 24)

123