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/external/u-boot/drivers/gpio/
DKconfig2 # GPIO infrastructure and drivers
5 menu "GPIO Support"
8 bool "Enable Driver Model for GPIO drivers"
11 Enable driver model for GPIO access. The standard GPIO
13 the GPIO uclass. Drivers provide methods to query the
25 bool "BCM6345 GPIO driver"
28 This driver supports the GPIO banks on BCM6345 SoCs.
31 bool "DWAPB GPIO driver"
35 Support for the Designware APB GPIO driver.
38 bool "AT91 PIO GPIO driver"
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/external/u-boot/arch/x86/include/asm/arch-tangier/acpi/
Dsouthcluster.asl33 /* GPIO Low Memory Region */
88 GPIO
105 If (^^GPIO.AVBL == One)
107 ^^GPIO.WFD3 = One
119 GPIO
134 If (^^^GPIO.AVBL == One)
136 ^^^GPIO.WFD3 = Zero
145 If (^^^GPIO.AVBL == One)
147 ^^^GPIO.WFD3 = One
175 "\\_SB.PCI0.GPIO", 0, ResourceConsumer, , ) { 110 }
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/external/u-boot/arch/arm/dts/
Dhi3798cv200-poplar.dts79 gpio-line-names = "LS-GPIO-E", "",
81 "", "LS-GPIO-F",
82 "", "LS-GPIO-J";
87 gpio-line-names = "LS-GPIO-H", "LS-GPIO-I",
88 "LS-GPIO-L", "LS-GPIO-G",
89 "LS-GPIO-K", "",
97 "LS-GPIO-C", "",
98 "", "LS-GPIO-B";
105 "", "LS-GPIO-D",
113 "", "LS-GPIO-A",
Dzynqmp-zcu100-revC.dts141 "", "GPIO-A", "GPIO-B", "SPI0_SCLK", "GPIO-C",
142 "GPIO-D", "SPI0_CS", "SPI0_MISO", "SPI_MOSI", "GPIO-E",
143 "GPIO-F", "SD1_D0", "SD1_D1", "SD1_D2", "SD1_D3",
/external/u-boot/doc/device-tree-bindings/gpio/
Dnvidia,tegra186-gpio.txt1 NVIDIA Tegra186 GPIO controllers
3 Tegra186 contains two GPIO controllers; a main controller and an "AON"
9 The Tegra186 GPIO controller allows software to set the IO direction of, and
10 read/write the value of, numerous GPIO signals. Routing of GPIO signals to
14 a) Security registers, which allow configuration of allowed access to the GPIO
17 varies between the different GPIO controllers.
20 that wishes to configure access to the GPIO registers needs access to these
21 registers to do so. Code which simply wishes to read or write GPIO data does not
24 b) GPIO registers, which allow manipulation of the GPIO signals. In some GPIO
27 documentation for rationale. Any particular GPIO client is expected to access
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Dgpio.txt1 Specifying GPIO information for devices
16 GPIO properties should be named "[<name>-]gpios", with <name> being the purpose
17 of this GPIO for the device. While a non-existent <name> is considered valid
21 GPIO properties can contain one or more GPIO phandles, but only in exceptional
30 The following example could be used to describe GPIO pins used as device enable
66 GPIO pin number, and GPIO flags as accepted by the "qe_pio_e" gpio-controller.
68 1.1) GPIO specifier best practices
71 A gpio-specifier should contain a flag indicating the GPIO polarity; active-
76 GPIO controller that achieves (or represents, for inputs) a logically asserted
79 the GPIO controller and the device, then the gpio-specifier will represent the
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Dgpio-msm.txt1 Qualcomm Snapdragon GPIO controller
9 - gpio-controller : Marks the device node as a GPIO controller.
10 - gpio-count: Number of GPIO pins.
Daltera_pio.txt1 Altera GPIO controller bindings
9 - altr,gpio-bank-width: Width of the GPIO bank. This defines how many pins the
10 GPIO device has. Ranges between 1-32. Optional and defaults to 32 if not
Dnvidia,tegra20-gpio.txt1 NVIDIA Tegra GPIO controller
12 - gpio-controller : Marks the device node as a GPIO controller.
14 The first cell is the GPIO number.
Dintel,x86-pinctrl.txt1 Intel x86 PINCTRL/GPIO controller
15 - mode-gpio - (optional) standalone property to force the pin into GPIO mode
19 - output-value - (optional) this set the default output value of the GPIO
/external/u-boot/doc/device-tree-bindings/pinctrl/
Dmarvell,armada-37xx-pinctrl.txt1 * Marvell Armada 37xx SoC pin and GPIO controller
3 Each Armada 37xx SoC comes with two pin and GPIO controllers, one for the
6 GPIO and pin controller:
21 - reg: The first set of registers is for pinctrl/GPIO and the second
23 - interrupts: list of interrupts used by the GPIO
141 GPIO subnode:
144 and the common GPIO bindings used by client devices.
146 Required properties for the GPIO driver under the gpio subnode:
148 - gpio-controller: Marks the device node as a GPIO controller.
149 - #gpio-cells: Should be 2. The first cell is the GPIO number and the
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Dst,stm32-pinctrl.txt1 * STM32 GPIO and Pin Mux/Config controller
3 STMicroelectronics's STM32 MCUs intregrate a GPIO and Pin mux/config hardware
20 GPIO controller/bank node:
22 - gpio-controller : Indicates this device is a GPIO controller
36 GPIO interrupts are forwarded to.
86 * 0 : GPIO IN
93 * 18 : GPIO OUT
/external/u-boot/board/intel/cherryhill/
Dcherryhill.c29 GPIO_PAD_CONF("N48: GP_CAMERASB00", GPIO, M1, GPO, LOW,
32 GPIO_PAD_CONF("N53: GP_CAMERASB01", GPIO, M1, GPO, LOW,
35 GPIO_PAD_CONF("N46: GP_CAMERASB02", GPIO, M1, GPO, LOW,
38 GPIO_PAD_CONF("N51: GP_CAMERASB03", GPIO, M1, GPO, LOW,
41 GPIO_PAD_CONF("N56: GP_CAMERASB04", GPIO, M1, GPO, LOW,
44 GPIO_PAD_CONF("N45: GP_CAMERASB05", GPIO, M1, GPO, LOW,
47 GPIO_PAD_CONF("N49: GP_CAMERASB06", GPIO, M1, GPO, LOW,
50 GPIO_PAD_CONF("N54: GP_CAMERASB07", GPIO, M1, GPO, LOW,
53 GPIO_PAD_CONF("N47: GP_CAMERASB08", GPIO, M1, GPO, LOW,
56 GPIO_PAD_CONF("N52: GP_CAMERASB09", GPIO, M1, GPO, LOW,
[all …]
/external/u-boot/doc/device-tree-bindings/spi/
Dsoft-spi.txt3 The soft SPI bus implementation allows the use of GPIO pins to simulate a
12 gpio-sck: GPIO to use for SPI clock (output)
14 gpio-mosi: GPIO to use for SPI MOSI line (output)
15 gpio-miso: GPIO to use for SPI MISO line (input)
20 The GPIOs should be specified as required by the GPIO controller referenced.
22 typically holds the GPIO number.
/external/u-boot/drivers/pinctrl/renesas/
DKconfig17 the GPIO definitions and pin control functions for each available
28 the GPIO definitions and pin control functions for each available
39 the GPIO definitions and pin control functions for each available
50 the GPIO definitions and pin control functions for each available
61 the GPIO definitions and pin control functions for each available
72 the GPIO definitions and pin control functions for each available
83 the GPIO definitions and pin control functions for each available
94 the GPIO definitions and pin control functions for each available
105 the GPIO definitions and pin control functions for each available
116 the GPIO definitions and pin control functions for each available
/external/u-boot/doc/device-tree-bindings/video/
Dtegra20-dc.txt33 Optional GPIO properies all have (phandle, GPIO number, flags):
34 - nvidia,backlight-enable-gpios: backlight enable GPIO
35 - nvidia,lvds-shutdown-gpios: LVDS power shutdown GPIO
36 - nvidia,backlight-vdd-gpios: backlight power GPIO
37 - nvidia,panel-vdd-gpios: panel power GPIO
/external/u-boot/drivers/i2c/muxes/
DKconfig20 bool "GPIO-based I2C arbitration"
26 a GPIO.
39 tristate "GPIO-based I2C multiplexer"
43 a GPIO based I2C multiplexer. This driver provides access to
45 through GPIO pins.
/external/u-boot/arch/mips/mach-bmips/
DKconfig134 ethernet ports, 1 USB port, 1 UART, GPIO buttons and LEDs, and
145 ethernet ports, 1 USB port, 1 UART, GPIO buttons and LEDs, and
156 ethernet ports, 1 USB port, 1 UART, GPIO buttons and LEDs, and a
167 ethernet ports, 1 USB port, 1 UART, GPIO buttons and LEDs,
178 ethernet ports, 1 USB port, 1 UART, GPIO buttons and LEDs,
189 ethernet ports, 3 USB ports, 1 UART, GPIO buttons and LEDs, and
200 ethernet ports, 1 UART, GPIO buttons and LEDs, and a BCM43225
211 ethernet ports, 2 USB ports, 1 UART, GPIO buttons and LEDs, and a
222 ethernet ports, 1 UART, GPIO buttons and LEDs, and a BCM4312
233 ethernet ports, 2 USB ports, 1 UART, GPIO buttons and LEDs, and
/external/u-boot/drivers/pinctrl/
DKconfig115 both the GPIO definitions and pin control functions for each
149 contains both GPIO defintion and pin control functions.
158 the GPIO definitions and pin control functions for each available
168 the GPIO definitions and pin control functions for each available
178 the GPIO definitions and pin control functions for each available
188 the GPIO definitions and pin control functions for each available
198 the GPIO definitions and pin control functions for each available
208 the GPIO definitions and pin control functions for each available
218 the GPIO definitions and pin control functions for each available
228 the GPIO definitions and pin control functions for each available
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/external/u-boot/board/keymile/km_arm/
Dkwbimage_256M8_1.cfg30 # bit 3-0: 0, MPPSel8 GPIO[8] CPU_SDA bitbanged
31 # bit 7-4: 0, MPPSel9 GPIO[9] CPU_SCL bitbanged
35 # bit 23-20: 3, MPPSel13 GPIO[14]
36 # bit 27-24: 3, MPPSel14 GPIO[15]
37 # bit 31-28: 0, MPPSel15 GPIO[16] BOOT_FL_SEL (SPI-MUX Signal)
40 # bit 3-0: 0, MPPSel16 GPIO[16]
44 # bit 19-16: 0, MPPSel20 GPIO[20]
45 # bit 23-20: 0, MPPSel21 GPIO[21]
46 # bit 27-24: 0, MPPSel22 GPIO[22]
47 # bit 31-28: 0, MPPSel23 GPIO[23]
Dkwbimage.cfg25 # bit 3-0: MPPSel16 0, GPIO[16]
26 # bit 7-4: MPPSel17 0, GPIO[17]
29 # bit 19-16: MPPSel20 0, GPIO[20]
30 # bit 23-20: MPPSel21 0, GPIO[21]
31 # bit 27-24: MPPSel22 0, GPIO[22]
32 # bit 31-28: MPPSel23 0, GPIO[23]
Dkwbimage_128M16_1.cfg30 # bit 3-0: 0, MPPSel8 GPIO[8]
31 # bit 7-4: 0, MPPSel9 GPIO[9]
37 # bit 31-28: 0, MPPSel15 GPIO[15]
40 # bit 3-0: 0, MPPSel16 GPIO[16]
44 # bit 19-16: 0, MPPSel20 GPIO[20]
45 # bit 23-20: 0, MPPSel21 GPIO[21]
46 # bit 27-24: 0, MPPSel22 GPIO[22]
47 # bit 31-28: 0, MPPSel23 GPIO[23]
Dkwbimage-memphis.cfg28 # bit 3-0: MPPSel16 0, GPIO[16]
29 # bit 7-4: MPPSel17 0, GPIO[17]
32 # bit 19-16: MPPSel20 0, GPIO[20]
33 # bit 23-20: MPPSel21 0, GPIO[21]
34 # bit 27-24: MPPSel22 0, GPIO[22]
35 # bit 31-28: MPPSel23 0, GPIO[23]
/external/u-boot/arch/x86/include/asm/arch-baytrail/acpi/
Dgpio.asl9 /* SouthCluster GPIO */
38 /* NorthCluster GPIO */
67 /* SUS GPIO */
/external/u-boot/doc/device-tree-bindings/leds/
Dleds-gpio.txt1 LEDs connected to GPIO lines
10 - gpios : Should specify the LED's GPIO, see "gpios property" in
12 indicated using flags in the GPIO specifier.

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