Searched refs:HHI_GCLK_MPEG2 (Results 1 – 2 of 2) sorted by relevance
| /external/u-boot/drivers/clk/ |
| D | clk_meson.c | 76 MESON_GATE(CLKID_AHB_DATA_BUS, HHI_GCLK_MPEG2, 1),
77 MESON_GATE(CLKID_AHB_CTRL_BUS, HHI_GCLK_MPEG2, 2),
78 MESON_GATE(CLKID_HDMI_INTR_SYNC, HHI_GCLK_MPEG2, 3),
79 MESON_GATE(CLKID_HDMI_PCLK, HHI_GCLK_MPEG2, 4),
80 MESON_GATE(CLKID_USB1_DDR_BRIDGE, HHI_GCLK_MPEG2, 8),
81 MESON_GATE(CLKID_USB0_DDR_BRIDGE, HHI_GCLK_MPEG2, 9),
82 MESON_GATE(CLKID_MMC_PCLK, HHI_GCLK_MPEG2, 11),
83 MESON_GATE(CLKID_DVIN, HHI_GCLK_MPEG2, 12),
84 MESON_GATE(CLKID_UART2, HHI_GCLK_MPEG2, 15),
85 MESON_GATE(CLKID_SANA, HHI_GCLK_MPEG2, 22),
[all …]
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| /external/u-boot/arch/arm/include/asm/arch-meson/ |
| D | clock.h | 37 #define HHI_GCLK_MPEG2 0x148 /* 0x52 offset in data sheet */ macro
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