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Searched refs:HHI_MPLL_CNTL (Results 1 – 2 of 2) sorted by relevance

/external/u-boot/drivers/clk/
Dclk_meson.c267 {HHI_MPLL_CNTL, 0, 9}, /* pm */
268 {HHI_MPLL_CNTL, 9, 5}, /* pn */
269 {HHI_MPLL_CNTL, 16, 2}, /* pod */
/external/u-boot/arch/arm/include/asm/arch-meson/
Dclock.h74 #define HHI_MPLL_CNTL 0x280 /* 0xa0 offset in data sheet */ macro