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Searched refs:HasV6T2Ops (Results 1 – 20 of 20) sorted by relevance

/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMSubtarget.cpp46 , HasV6T2Ops(false) in ARMSubtarget()
97 if (!HasV6T2Ops && hasThumb2()) in ARMSubtarget()
98 HasV4TOps = HasV5TOps = HasV5TEOps = HasV6Ops = HasV6T2Ops = true; in ARMSubtarget()
DARM.td113 def HasV6T2Ops : SubtargetFeature<"v6t2", "HasV6T2Ops", "true",
118 [HasV6T2Ops]>;
195 def : Processor<"arm1156t2-s", ARMV6Itineraries, [HasV6T2Ops,
197 def : Processor<"arm1156t2f-s", ARMV6Itineraries, [HasV6T2Ops, FeatureVFP2,
DARMSubtarget.h45 bool HasV6T2Ops; variable
192 bool hasV6T2Ops() const { return HasV6T2Ops; } in hasV6T2Ops()
DARMInstrInfo.td178 AssemblerPredicate<"HasV6T2Ops">;
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/MCTargetDesc/
DARMAsmBackend.h39 bool hasNOP() const { return STI.getFeatureBits()[ARM::HasV6T2Ops]; } in hasNOP()
DARMTargetStreamer.cpp134 } else if (STI.hasFeature(ARM::HasV6T2Ops)) in getArchForCPU()
155 !STI.hasFeature(ARM::HasV6T2Ops)) || in isV8M()
/external/llvm/lib/Target/ARM/MCTargetDesc/
DARMAsmBackend.h37 bool hasNOP() const { return STI->getFeatureBits()[ARM::HasV6T2Ops]; } in hasNOP()
/external/llvm/lib/Target/ARM/
DARMSubtarget.h93 bool HasV6T2Ops = false; variable
399 bool hasV6T2Ops() const { return HasV6T2Ops; } in hasV6T2Ops()
DARM.td289 def HasV6T2Ops : SubtargetFeature<"v6t2", "HasV6T2Ops", "true",
294 [HasV6T2Ops, FeaturePerfMon,
390 def ARMv6t2 : Architecture<"armv6t2", "ARMv6t2", [HasV6T2Ops,
DARMInstrInfo.td207 AssemblerPredicate<"HasV6T2Ops", "armv6t2">;
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/
DARMSubtarget.h149 bool HasV6T2Ops = false; variable
525 bool hasV6T2Ops() const { return HasV6T2Ops; } in hasV6T2Ops()
DARM.td409 def HasV6T2Ops : SubtargetFeature<"v6t2", "HasV6T2Ops", "true",
415 [HasV6T2Ops, FeaturePerfMon,
538 def ARMv6t2 : Architecture<"armv6t2", "ARMv6t2", [HasV6T2Ops,
DARMInstrInfo.td239 AssemblerPredicate<"HasV6T2Ops", "armv6t2">;
/external/swiftshader/third_party/LLVM/lib/Target/ARM/MCTargetDesc/
DARMAsmBackend.cpp54 return (STI->getFeatureBits() & ARM::HasV6T2Ops) != 0; in hasNOP()
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/ARM/
DARMGenSubtargetInfo.inc125 HasV6T2Ops = 109,
211 { "armv6t2", "ARMv6t2 architecture", { ARM::ARMv6t2 }, { ARM::HasV6T2Ops, ARM::FeatureDSP } },
304 …{ "v6t2", "Support ARM v6t2 instructions", { ARM::HasV6T2Ops }, { ARM::HasV8MBaselineOps, ARM::Has…
305 …{ "v7", "Support ARM v7 instructions", { ARM::HasV7Ops }, { ARM::HasV6T2Ops, ARM::FeaturePerfMon, …
16604 if (Bits[ARM::HasV6T2Ops]) HasV6T2Ops = true;
DARMGenMCCodeEmitter.inc11197 if ((FB[ARM::HasV6T2Ops]))
DARMGenDisassemblerTables.inc11237 return (!Bits[ARM::ModeThumb] && Bits[ARM::HasV6T2Ops]);
DARMGenAsmMatcher.inc7647 if ((FB[ARM::HasV6T2Ops]))
/external/llvm/lib/Target/ARM/AsmParser/
DARMAsmParser.cpp267 return getSTI().getFeatureBits()[ARM::HasV6T2Ops]; in hasV6T2Ops()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/AsmParser/
DARMAsmParser.cpp458 return getSTI().getFeatureBits()[ARM::HasV6T2Ops]; in hasV6T2Ops()