Searched refs:HiHalf (Results 1 – 4 of 4) sorted by relevance
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/ |
| D | HexagonISelDAGToDAGHVX.cpp | 630 return OpRef(R.OpN & (Undef | Index | HiHalf)); in hi()
647 HiHalf = 0x40000000, enumerator
648 Whole = LoHalf | HiHalf,
720 assert((OpN & Whole) == LoHalf || (OpN & Whole) == HiHalf); in print()
1006 assert(Part == OpRef::LoHalf || Part == OpRef::HiHalf); in materialize()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| D | SIInstrInfo.cpp | 4271 MachineInstr *HiHalf = in splitScalar64BitAddSub() local
4289 legalizeOperands(*HiHalf); in splitScalar64BitAddSub()
4340 MachineInstr &HiHalf = *BuildMI(MBB, MII, DL, InstDesc, DestSub1) in splitScalar64BitBinaryOp() local
4356 legalizeOperands(HiHalf); in splitScalar64BitBinaryOp()
|
| D | SIISelLowering.cpp | 4220 SDValue HiHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, BCVec, in lowerINSERT_VECTOR_ELT() local
4224 SDValue HiVec = DAG.getNode(ISD::BITCAST, SL, MVT::v2i16, HiHalf); in lowerINSERT_VECTOR_ELT()
4236 DAG.getBuildVector(MVT::v2i32, SL, { InsHalf, HiHalf }) : in lowerINSERT_VECTOR_ELT()
|
| /external/llvm/lib/Target/AMDGPU/ |
| D | SIInstrInfo.cpp | 2794 MachineInstr &HiHalf = *BuildMI(MBB, MII, DL, InstDesc, DestSub1) in splitScalar64BitBinaryOp() local
2810 legalizeOperands(HiHalf); in splitScalar64BitBinaryOp()
|