Searched refs:INS0 (Results 1 – 4 of 4) sorted by relevance
| /external/llvm/lib/Fuzzer/test/ |
| D | FuzzerUnittest.cpp | 133 uint8_t INS0[8] = {0xF1, 0x00, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66}; in TestInsertByte() local
144 if (NewSize == 8 && !memcmp(INS0, T, 8)) FoundMask |= 1 << 0; in TestInsertByte()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/ |
| D | indirect-addressing-si.ll | 386 ; GCN-DAG: v_mov_b32 [[INS0:v[0-9]+]], 62
400 ; MOVREL-NEXT: v_movreld_b32_e32 v[[VEC_ELT0]], [[INS0]]
403 ; IDXMODE-NEXT: v_mov_b32_e32 v[[VEC_ELT0]], [[INS0]]
431 ; GCN: buffer_store_dword [[INS0]]
|
| D | amdgpu-codegenprepare-fdiv.ll | 87 ; CHECK: %[[INS0:[0-9]+]] = insertelement <2 x float> undef, float %[[FDIV0]], i64 0
91 ; CHECK: %md.25ulp = insertelement <2 x float> %[[INS0]], float %[[FDIV1]], i64 1
|
| /external/llvm/test/CodeGen/AMDGPU/ |
| D | indirect-addressing-si.ll | 263 ; CHECK-DAG: v_mov_b32 [[INS0:v[0-9]+]], 62
273 ; CHECK-NEXT: v_movreld_b32_e32 v[[MOVREL0:[0-9]+]], [[INS0]]
293 ; CHECK: buffer_store_dword [[INS0]]
|