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Searched refs:INTEL_MASK (Results 1 – 6 of 6) sorted by relevance

/external/mesa3d/src/mesa/drivers/dri/i965/
Dbrw_defines.h37 #define INTEL_MASK(high, low) (((1u<<((high)-(low)+1))-1)<<(low)) macro
46 #define GET_BITS(data, high, low) ((data & INTEL_MASK((high), (low))) >> (low))
261 #define BRW_SURFACE_FORMAT_MASK INTEL_MASK(26, 18)
267 #define BRW_SURFACE_TYPE_MASK INTEL_MASK(31, 29)
288 #define GEN8_SURFACE_MOCS_MASK INTEL_MASK(30, 24)
290 #define GEN8_SURFACE_QPITCH_MASK INTEL_MASK(14, 0)
294 #define BRW_SURFACE_HEIGHT_MASK INTEL_MASK(31, 19)
296 #define BRW_SURFACE_WIDTH_MASK INTEL_MASK(18, 6)
298 #define BRW_SURFACE_LOD_MASK INTEL_MASK(5, 2)
300 #define GEN7_SURFACE_HEIGHT_MASK INTEL_MASK(29, 16)
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/external/mesa3d/src/intel/compiler/
Dbrw_nir.h161 #define BRW_NIR_FRAG_OUTPUT_INDEX_MASK INTEL_MASK(0, 0)
163 #define BRW_NIR_FRAG_OUTPUT_LOCATION_MASK INTEL_MASK(31, 1)
Dbrw_eu_defines.h40 #define INTEL_MASK(high, low) (((1u<<((high)-(low)+1))-1)<<(low)) macro
49 #define GET_BITS(data, high, low) ((data & INTEL_MASK((high), (low))) >> (low))
Dbrw_vec4_generator.cpp759 const int mask = ivb ? INTEL_MASK(22, 16) : INTEL_MASK(23, 17); in generate_tcs_get_instance_id()
1067 brw_imm_ud(ivb ? INTEL_MASK(15, 12) : INTEL_MASK(16, 13))); in generate_tcs_create_barrier_header()
Dbrw_fs_nir.cpp2488 brw_imm_ud(INTEL_MASK(16, 13))); in nir_emit_tcs_intrinsic()
Dbrw_fs.cpp6263 brw_imm_ud(INTEL_MASK(23, 17))); in run_tcs_single_patch()