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Searched refs:IP3_3_0 (Results 1 – 6 of 6) sorted by relevance

/external/u-boot/drivers/pinctrl/renesas/
Dpfc-r8a77970.c104 #define GPSR2_1 F_(VI0_CLKENB, IP3_3_0)
177 #define IP3_3_0 FM(VI0_CLKENB) FM(MSIOF2_RXD) FM(RX3) FM(RD_WR_N) FM(HCTS3_N) F_(0, 0) F_(0, … macro
259 FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \
482 PINMUX_IPSR_GPSR(IP3_3_0, VI0_CLKENB),
483 PINMUX_IPSR_GPSR(IP3_3_0, MSIOF2_RXD),
484 PINMUX_IPSR_GPSR(IP3_3_0, RX3),
485 PINMUX_IPSR_GPSR(IP3_3_0, RD_WR_N),
486 PINMUX_IPSR_GPSR(IP3_3_0, HCTS3_N),
2297 IP3_3_0 }
Dpfc-r8a77990.c84 #define GPSR1_1 F_(A1, IP3_3_0)
213 #define IP3_3_0 FM(A1) FM(IRQ1) FM(PWM3_A) FM(DU_DOTCLKIN1) FM(VI5_DATA0_A) FM(DU_DISP_CDE) F… macro
361 FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \
635 PINMUX_IPSR_GPSR(IP3_3_0, A1),
636 PINMUX_IPSR_GPSR(IP3_3_0, IRQ1),
637 PINMUX_IPSR_MSEL(IP3_3_0, PWM3_A, SEL_PWM3_0),
638 PINMUX_IPSR_GPSR(IP3_3_0, DU_DOTCLKIN1),
639 PINMUX_IPSR_MSEL(IP3_3_0, VI5_DATA0_A, SEL_VIN5_0),
640 PINMUX_IPSR_GPSR(IP3_3_0, DU_DISP_CDE),
641 PINMUX_IPSR_MSEL(IP3_3_0, SDA6_B, SEL_I2C6_1),
[all …]
Dpfc-r8a77995.c62 #define GPSR1_17 F_(DU_DR1, IP3_3_0)
225 #define IP3_3_0 FM(DU_DR1) FM(LCDOUT17) FM(TX4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)… macro
351 FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \
620 PINMUX_IPSR_GPSR(IP3_3_0, DU_DR1),
621 PINMUX_IPSR_GPSR(IP3_3_0, LCDOUT17),
622 PINMUX_IPSR_MSEL(IP3_3_0, TX4_B, SEL_SCIF4_1),
2299 IP3_3_0 }
Dpfc-r8a7796.c82 #define GPSR1_9 F_(A9, IP3_3_0)
242 #define IP3_3_0 FM(A9) F_(0, 0) FM(MSIOF2_SCK_A) FM(CTS4_N_B) F_(0, 0) FM(VI5_VSYNC_N) F_(0, 0… macro
409 FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \
759 PINMUX_IPSR_GPSR(IP3_3_0, A9),
760 PINMUX_IPSR_MSEL(IP3_3_0, MSIOF2_SCK_A, SEL_MSIOF2_0),
761 PINMUX_IPSR_MSEL(IP3_3_0, CTS4_N_B, SEL_SCIF4_1),
762 PINMUX_IPSR_GPSR(IP3_3_0, VI5_VSYNC_N),
5337 IP3_3_0 }
Dpfc-r8a7795.c76 #define GPSR1_9 F_(A9, IP3_3_0)
238 #define IP3_3_0 FM(A9) F_(0, 0) FM(MSIOF2_SCK_A) FM(CTS4_N_B) F_(0, 0) FM(VI5_VSYNC_N) F_(0, 0… macro
403 FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \
757 PINMUX_IPSR_GPSR(IP3_3_0, A9),
758 PINMUX_IPSR_MSEL(IP3_3_0, MSIOF2_SCK_A, SEL_MSIOF2_0),
759 PINMUX_IPSR_MSEL(IP3_3_0, CTS4_N_B, SEL_SCIF4_1),
760 PINMUX_IPSR_GPSR(IP3_3_0, VI5_VSYNC_N),
5393 IP3_3_0 }
Dpfc-r8a7790.c941 PINMUX_IPSR_GPSR(IP3_3_0, A11),
942 PINMUX_IPSR_MSEL(IP3_3_0, SCIFB2_CTS_N_B, SEL_SCIFB2_1),
943 PINMUX_IPSR_GPSR(IP3_3_0, MSIOF2_SCK),
944 PINMUX_IPSR_MSEL(IP3_3_0, VI1_R0, SEL_VI1_0),
945 PINMUX_IPSR_MSEL(IP3_3_0, VI1_R0_B, SEL_VI1_1),
946 PINMUX_IPSR_GPSR(IP3_3_0, VI2_G0),
947 PINMUX_IPSR_MSEL(IP3_3_0, VI2_DATA3_VI2_B3_B, SEL_VI2_1),