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Searched refs:IP7_3_0 (Results 1 – 5 of 5) sorted by relevance

/external/u-boot/drivers/pinctrl/renesas/
Dpfc-r8a77970.c108 #define GPSR3_16 F_(VI1_FIELD, IP7_3_0)
209 #define IP7_3_0 FM(VI1_FIELD) FM(SDA4) FM(IRQ5) FM(D15) FM(MMC_CD) F_(0, 0) F_(0, 0) F_(0, 0)… macro
268 FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \
638 PINMUX_IPSR_GPSR(IP7_3_0, VI1_FIELD),
639 PINMUX_IPSR_GPSR(IP7_3_0, SDA4),
640 PINMUX_IPSR_GPSR(IP7_3_0, IRQ5),
641 PINMUX_IPSR_GPSR(IP7_3_0, D15),
642 PINMUX_IPSR_GPSR(IP7_3_0, MMC_CD),
2337 IP7_3_0 }
Dpfc-r8a77990.c49 #define GPSR0_11 F_(D11, IP7_3_0)
247 #define IP7_3_0 FM(D11) FM(MSIOF2_TXD_A) F_(0, 0) F_(0, 0) FM(VI5_DATA11_A) FM(DU_DG2) FM(RIF3… macro
370 FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \
889 PINMUX_IPSR_GPSR(IP7_3_0, D11),
890 PINMUX_IPSR_GPSR(IP7_3_0, MSIOF2_TXD_A),
891 PINMUX_IPSR_MSEL(IP7_3_0, VI5_DATA11_A, SEL_VIN5_0),
892 PINMUX_IPSR_GPSR(IP7_3_0, DU_DG2),
893 PINMUX_IPSR_MSEL(IP7_3_0, RIF3_D1_B, SEL_DRIF3_1),
894 PINMUX_IPSR_MSEL(IP7_3_0, HRTS3_N_E, SEL_HSCIF3_4),
895 PINMUX_IPSR_GPSR(IP7_3_0, LCDOUT10),
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Dpfc-r8a77995.c94 #define GPSR2_19 F_(VI4_DATA18, IP7_3_0)
259 #define IP7_3_0 FM(VI4_DATA18) FM(HSCK3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, … macro
360 FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \
735 PINMUX_IPSR_GPSR(IP7_3_0, VI4_DATA18),
736 PINMUX_IPSR_MSEL(IP7_3_0, HSCK3_A, SEL_HSCIF3_0),
2339 IP7_3_0 }
Dpfc-r8a7796.c47 #define GPSR0_13 F_(D13, IP7_3_0)
278 #define IP7_3_0 FM(D13) FM(LCDOUT5) FM(MSIOF2_SS2_D) FM(TX4_C) FM(VI4_DATA5_A) F_(0, 0) FM(DU_… macro
418 FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \
961 PINMUX_IPSR_GPSR(IP7_3_0, D13),
962 PINMUX_IPSR_GPSR(IP7_3_0, LCDOUT5),
963 PINMUX_IPSR_MSEL(IP7_3_0, MSIOF2_SS2_D, SEL_MSIOF2_3),
964 PINMUX_IPSR_MSEL(IP7_3_0, TX4_C, SEL_SCIF4_2),
965 PINMUX_IPSR_MSEL(IP7_3_0, VI4_DATA5_A, SEL_VIN4_0),
966 PINMUX_IPSR_GPSR(IP7_3_0, DU_DR5),
5377 IP7_3_0 }
Dpfc-r8a7795.c41 #define GPSR0_13 F_(D13, IP7_3_0)
270 #define IP7_3_0 FM(D13) FM(LCDOUT5) FM(MSIOF2_SS2_D) FM(TX4_C) FM(VI4_DATA5_A) F_(0, 0) FM(DU_… macro
412 FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \
959 PINMUX_IPSR_GPSR(IP7_3_0, D13),
960 PINMUX_IPSR_GPSR(IP7_3_0, LCDOUT5),
961 PINMUX_IPSR_MSEL(IP7_3_0, MSIOF2_SS2_D, SEL_MSIOF2_3),
962 PINMUX_IPSR_MSEL(IP7_3_0, TX4_C, SEL_SCIF4_2),
963 PINMUX_IPSR_MSEL(IP7_3_0, VI4_DATA5_A, SEL_VIN4_0),
964 PINMUX_IPSR_GPSR(IP7_3_0, DU_DR5),
5433 IP7_3_0 }