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Searched refs:ISA (Results 1 – 25 of 258) sorted by relevance

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/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/mips3/
D	invalid-mips4.s	9 … # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level 32 …$f7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level 34 …$f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level 36 …$f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level 38 …$f2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level 40 …$f7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level 42 …$f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level 44 …$f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level 46 …$f4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level 48 …$f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level [all …]
D	invalid-mips5.s	9 … # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level 34 …$f7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level 36 …$f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level 38 …$f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level 40 …$f2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level 42 …$f7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level 44 …$f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level 46 …$f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level 48 …$f4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level 50 …$f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level [all …]
/external/libdivsufsort/lib/
D	trsort.c	264 tr_copy(saidx_t ISA, const saidx_t SA, in tr_copy() argument 274 if((0 <= (s = c - depth)) && (ISA[s] == v)) { in tr_copy() 276 ISA[s] = d - SA; in tr_copy() 280 if((0 <= (s = c - depth)) && (ISA[s] == v)) { in tr_copy() 282 ISA[s] = d - SA; in tr_copy() 289 tr_partialcopy(saidx_t ISA, const saidx_t SA, in tr_partialcopy() argument 299 if((0 <= (s = c - depth)) && (ISA[s] == v)) { in tr_partialcopy() 301 rank = ISA[s + depth]; in tr_partialcopy() 303 ISA[s] = newrank; in tr_partialcopy() 309 rank = ISA[e]; in tr_partialcopy() [all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/mips1/
D	invalid-mips5-wrong-error.s	48 … # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level 50 … # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level 52 … # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level 54 … # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level 56 … # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level 58 … # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level 60 … # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level 62 … # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level 64 … # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level 66 … # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level [all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/mips2/
D	invalid-mips32.s	9 … # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level 47 …$f7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level 49 …$f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level 51 …$f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level 53 …$f2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level 55 …$f7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level 57 …$f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level 59 …$f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level 61 …$f4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level 63 …$f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level [all …]
D	invalid-mips5.s	9 … # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level 75 …$f7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level 77 …$f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level 79 …$f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level 81 …$f2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level 83 …$f7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level 85 …$f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level 87 …$f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level 89 …$f4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level 91 …$f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level [all …]
D	invalid-mips32r2.s	9 … # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level 15 …7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level 17 …6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level 19 …6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level 21 …2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level 23 …7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level 25 …6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level 27 …6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level 29 …4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level 31 …8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level [all …]
/external/llvm/lib/Target/Mips/
D	Mips.td	`31 // Predicates for the instruction group membership such as ISA's and ASE's 88 "Mips I ISA Support [highly experimental]">; 90 "Mips II ISA Support [highly experimental]", 99 "MIPS III ISA Support [highly experimental]", 110 "Mips4", "MIPS IV ISA Support", 117 "MIPS V ISA Support [highly experimental]", 120 "Mips32 ISA Support", 124 "Mips32r2", "Mips32r2 ISA Support", 128 "Mips32r3", "Mips32r3 ISA Support", 131 "Mips32r5", "Mips32r5 ISA Support", [all …]`
/external/u-boot/arch/arc/
D	Kconfig	`16 bool "ARCompact ISA" 18 The original ARC ISA of ARC600/700 cores 21 bool "ARC ISA v2" 23 ISA for the Next Generation ARC-HS cores 51 Next Generation ARC Core based on ISA-v2 ISA without MMU. 58 Next Generation ARC Core based on ISA-v2 ISA without MMU. 65 Next Generation ARC Core based on ISA-v2 ISA with MMU.`
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/
D	Mips.td	`31 // Predicates for the instruction group membership such as ISA's. 96 "Mips I ISA Support [highly experimental]">; 98 "Mips II ISA Support [highly experimental]", 107 "MIPS III ISA Support [highly experimental]", 118 "Mips4", "MIPS IV ISA Support", 125 "MIPS V ISA Support [highly experimental]", 128 "Mips32 ISA Support", 132 "Mips32r2", "Mips32r2 ISA Support", 136 "Mips32r3", "Mips32r3 ISA Support", 139 "Mips32r5", "Mips32r5 ISA Support", [all …]`
/external/llvm/test/tools/llvm-readobj/
D	mips-abiflags.test	`8 EL64-NEXT: ISA: MIPS64r5 9 EL64-NEXT: ISA Extension: Cavium Networks Octeon3 (0x13) 27 BE32-NEXT: ISA: MIPS32r2 28 BE32-NEXT: ISA Extension: None (0x0)`
/external/swiftshader/third_party/llvm-7.0/llvm/test/tools/llvm-readobj/
D	mips-abiflags.test	`8 EL64-NEXT: ISA: MIPS64r5 9 EL64-NEXT: ISA Extension: Cavium Networks Octeon3 (0x13) 27 BE32-NEXT: ISA: MIPS32r2 28 BE32-NEXT: ISA Extension: None (0x0)`
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/
D	mips_abi_flags_xx.s	`41 # CHECK-OBJ-32R1-NEXT: ISA: {{MIPS32$}} 42 # CHECK-OBJ-32R6-NEXT: ISA: MIPS32r6 43 # CHECK-OBJ-64R2-NEXT: ISA: MIPS64r2 44 # CHECK-OBJ-MIPS-NEXT: ISA Extension: None (0x0) 45 # CHECK-OBJ-OCTEON-NEXT: ISA Extension: Cavium Networks Octeon (0x5)`
/external/llvm/test/MC/Mips/
D	mips_abi_flags_xx.s	`41 # CHECK-OBJ-32R1-NEXT: ISA: {{MIPS32$}} 42 # CHECK-OBJ-32R6-NEXT: ISA: MIPS32r6 43 # CHECK-OBJ-64R2-NEXT: ISA: MIPS64r2 44 # CHECK-OBJ-MIPS-NEXT: ISA Extension: None (0x0) 45 # CHECK-OBJ-OCTEON-NEXT: ISA Extension: Cavium Networks Octeon (0x5)`
/external/archive-patcher/generator/src/main/java/com/google/archivepatcher/generator/bsdiff/
D	DivSuffixSorter.java	1309 private final void trSort(int ISA, int n, int depth) throws IOException, InterruptedException { in trSort() argument 1314 for (ISAd = ISA + depth; -n < readSuffixArray(0); ISAd += ISAd - ISA) { in trSort() 1330 last = readSuffixArray(ISA + t) + 1; in trSort() 1333 trIntroSort(ISA, ISAd, first, last, budget); in trSort() 1415 private final void trIntroSort(int ISA, int ISAd, int first, int last, TRBudget budget) in trIntroSort() argument 1421 int incr = ISAd - ISA; in trIntroSort() 1434 writeSuffixArray(ISA + readSuffixArray(c), v); in trIntroSort() 1439 writeSuffixArray(ISA + readSuffixArray(c), v); in trIntroSort() 1496 trCopy(ISA, first, a, b, last, ISAd - ISA); in trIntroSort() 1501 trPartialCopy(ISA, first, a, b, last, ISAd - ISA); in trIntroSort() [all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/
D	elf-notes.ll	`19 ; OSABI-UNK-ELF: NT_AMD_AMDGPU_ISA (ISA Version) 20 ; OSABI-UNK-ELF: ISA Version: 36 ; OSABI-HSA-ELF: NT_AMD_AMDGPU_ISA (ISA Version) 37 ; OSABI-HSA-ELF: ISA Version: 63 ; OSABI-PAL-ELF: NT_AMD_AMDGPU_ISA (ISA Version) 64 ; OSABI-PAL-ELF: ISA Version:`
D	README	`9 ISA instruction, then that test should go in a file called {ISA_name}.ll (e.g. 20 the file is named after a DAG opcode or ISA instruction that has an`
/external/llvm/lib/Target/AMDGPU/Utils/
D	AMDGPUBaseInfo.cpp	`53 IsaVersion ISA = getIsaVersion(Features); in initDefaultAMDKernelCodeT() local 60 Header.amd_machine_version_major = ISA.Major; in initDefaultAMDKernelCodeT() 61 Header.amd_machine_version_minor = ISA.Minor; in initDefaultAMDKernelCodeT() 62 Header.amd_machine_version_stepping = ISA.Stepping; in initDefaultAMDKernelCodeT()`
/external/swiftshader/third_party/LLVM/lib/Target/Mips/
D	Mips.td	`62 "Mips32 ISA Support", 65 "Mips32r2", "Mips32r2 ISA Support", 68 "Mips64", "Mips64 ISA Support", 72 "Mips64r2", "Mips64r2 ISA Support",`
/external/llvm/docs/
D	CompilerWriterInfo.rst	69 * `AMD R6xx shader ISA <http://developer.amd.com/wordpress/media/2012/10/R600_Instruction_Set_Archi… 70 * `AMD R7xx shader ISA <http://developer.amd.com/wordpress/media/2012/10/R700-Family_Instruction_Se… 71 * `AMD Evergreen shader ISA <http://developer.amd.com/wordpress/media/2012/10/AMD_Evergreen-Family_… 72 * `AMD Cayman/Trinity shader ISA <http://developer.amd.com/wordpress/media/2012/10/AMD_HD_6900_Seri… 73 * `AMD Southern Islands Series ISA <http://developer.amd.com/wordpress/media/2012/12/AMD_Southern_I… 74 * `AMD Sea Islands Series ISA <http://developer.amd.com/wordpress/media/2013/07/AMD_Sea_Islands_Ins… 102 * `The XMOS XS1 Architecture (ISA) <https://www.xmos.com/en/download/public/The-XMOS-XS1-Architectu… 141 ISA and Driver API documentation
D	AMDGPUUsage.rst	`8 The AMDGPU back-end provides ISA code generation for AMD GPUs, starting with 43 all apply to the Southern Islands ISA, Sea Islands and Volcanic Islands 133 set architecture (ISA) version of the assembly program. 138 If no arguments are specified, then the assembler will derive the ISA version, 142 ISA version, vendor, and arch will all be stored in a single entry of the`
/external/ImageMagick/PerlMagick/quantum/
D	quantum.pm	`21 use vars qw($VERSION @ISA @EXPORT $AUTOLOAD); 28 @ISA = qw(Exporter DynaLoader);`
/external/ImageMagick/PerlMagick/
D	Magick.pm	`22 use vars qw($VERSION @ISA @EXPORT $AUTOLOAD); 29 @ISA = qw(Exporter DynaLoader);`
/external/u-boot/arch/arm/mach-bcm283x/
D	Kconfig	`44 This option creates a build targetting the ARM1176 ISA. 60 This option creates a build targetting the ARMv7/AArch32 ISA. 83 This option creates a build targetting the ARMv7/AArch32 ISA. 99 This option creates a build targetting the ARMv7/AArch32 ISA. 127 This option creates a build targetting the ARMv8/AArch64 ISA.`
/external/llvm/test/CodeGen/AMDGPU/
D	README	`9 ISA instruction, then that test should go in a file called {ISA_name}.ll (e.g. 20 the file is named after a DAG opcode or ISA instruction that has an`

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