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Searched refs:ImplicitDefine (Results 1 – 25 of 50) sorted by relevance

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/external/llvm/lib/Target/AMDGPU/
DSIFrameLowering.cpp249 .addReg(ScratchRsrcReg, RegState::ImplicitDefine); in emitPrologue()
253 .addReg(ScratchRsrcReg, RegState::ImplicitDefine); in emitPrologue()
257 .addReg(ScratchRsrcReg, RegState::ImplicitDefine); in emitPrologue()
261 .addReg(ScratchRsrcReg, RegState::ImplicitDefine); in emitPrologue()
DSIRegisterInfo.cpp601 .addReg(MI->getOperand(0).getReg(), RegState::ImplicitDefine); in eliminateFrameIndex()
624 .addReg(MI->getOperand(0).getReg(), RegState::ImplicitDefine); in eliminateFrameIndex()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/
DSIFrameLowering.cpp389 .addReg(ScratchRsrcReg, RegState::ImplicitDefine); in emitEntryFunctionScratchSetup()
411 .addReg(ScratchRsrcReg, RegState::ImplicitDefine); in emitEntryFunctionScratchSetup()
430 .addReg(ScratchRsrcReg, RegState::ImplicitDefine) in emitEntryFunctionScratchSetup()
453 .addReg(ScratchRsrcReg, RegState::ImplicitDefine); in emitEntryFunctionScratchSetup()
471 .addReg(ScratchRsrcReg, RegState::ImplicitDefine); in emitEntryFunctionScratchSetup()
479 .addReg(ScratchRsrcReg, RegState::ImplicitDefine); in emitEntryFunctionScratchSetup()
483 .addReg(ScratchRsrcReg, RegState::ImplicitDefine); in emitEntryFunctionScratchSetup()
489 .addReg(ScratchRsrcReg, RegState::ImplicitDefine); in emitEntryFunctionScratchSetup()
493 .addReg(ScratchRsrcReg, RegState::ImplicitDefine); in emitEntryFunctionScratchSetup()
DSIRegisterInfo.cpp904 MIB.addReg(SuperReg, RegState::ImplicitDefine); in restoreSGPR()
918 MIB.addReg(SuperReg, RegState::ImplicitDefine); in restoreSGPR()
947 MIB.addReg(MI->getOperand(0).getReg(), RegState::ImplicitDefine); in restoreSGPR()
DSILowerControlFlow.cpp198 .addReg(AMDGPU::EXEC, RegState::ImplicitDefine); in emitIf()
/external/llvm/lib/Target/SystemZ/
DSystemZElimCompare.cpp217 .addReg(SystemZ::CC, RegState::ImplicitDefine | RegState::Dead); in convertToBRCT()
231 .addReg(SystemZ::CC, RegState::ImplicitDefine); in convertToLoadAndTest()
449 .addReg(SystemZ::CC, RegState::ImplicitDefine | RegState::Dead); in fuseCompareOperations()
DSystemZShortenInst.cpp147 .addReg(SystemZ::CC, RegState::ImplicitDefine | RegState::Dead); in shortenOn001AddCC()
DSystemZFrameLowering.cpp269 MIB.addReg(Reg, RegState::ImplicitDefine); in restoreCalleeSavedRegisters()
/external/swiftshader/third_party/LLVM/lib/Target/Blackfin/
DBlackfinRegisterInfo.cpp146 .addReg(Reg, RegState::ImplicitDefine); in loadConstant()
151 .addReg(Reg, RegState::ImplicitDefine); in loadConstant()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/SystemZ/
DSystemZElimCompare.cpp239 MIB.addReg(SystemZ::CC, RegState::ImplicitDefine | RegState::Dead); in convertToBRCT()
575 RegState::ImplicitDefine | RegState::Dead); in fuseCompareOperations()
DSystemZShortenInst.cpp147 .addReg(SystemZ::CC, RegState::ImplicitDefine | RegState::Dead); in shortenOn001AddCC()
DSystemZFrameLowering.cpp277 MIB.addReg(Reg, RegState::ImplicitDefine); in restoreCalleeSavedRegisters()
/external/swiftshader/third_party/LLVM/include/llvm/CodeGen/
DMachineInstrBuilder.h37 ImplicitDefine = Implicit | Define, enumerator
/external/swiftshader/third_party/LLVM/lib/Target/SystemZ/
DSystemZFrameLowering.cpp346 MIB.addReg(Reg, RegState::ImplicitDefine); in restoreCalleeSavedRegisters()
/external/llvm/include/llvm/CodeGen/
DMachineInstrBuilder.h42 ImplicitDefine = Implicit | Define, enumerator
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/
DMachineInstrBuilder.h55 ImplicitDefine = Implicit | Define, enumerator
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMExpandPseudoInsts.cpp461 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead)); in ExpandVLD()
600 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead)); in ExpandLaneOp()
997 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead)); in ExpandMI()
/external/llvm/lib/Target/Mips/
DMipsFastISel.cpp707 Mips::FCC0, RegState::ImplicitDefine); in emitCmp()
1884 .addReg(Mips::HI0, RegState::ImplicitDefine | RegState::Dead) in fastEmitInst_rr()
1885 .addReg(Mips::LO0, RegState::ImplicitDefine | RegState::Dead); in fastEmitInst_rr()
DMipsSEISelDAGToDAG.cpp51 IsDef ? RegState::ImplicitDefine : RegState::Implicit | RegState::Undef; in addDSPCtrlRegOperands()
/external/llvm/lib/Target/ARM/
DARMExpandPseudoInsts.cpp446 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead)); in ExpandVLD()
590 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead)); in ExpandLaneOp()
1403 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead)); in ExpandMI()
DThumb2InstrInfo.cpp205 MIB.addReg(DestReg, RegState::ImplicitDefine); in loadRegFromStackSlot()
DARMBaseInstrInfo.cpp1096 MIB.addReg(DestReg, RegState::ImplicitDefine); in loadRegFromStackSlot()
1129 MIB.addReg(DestReg, RegState::ImplicitDefine); in loadRegFromStackSlot()
1150 MIB.addReg(DestReg, RegState::ImplicitDefine); in loadRegFromStackSlot()
1170 MIB.addReg(DestReg, RegState::ImplicitDefine); in loadRegFromStackSlot()
DARMFrameLowering.cpp1256 .addReg(SupReg, RegState::ImplicitDefine)); in emitAlignedDPRCS2Restores()
1271 .addReg(SupReg, RegState::ImplicitDefine)); in emitAlignedDPRCS2Restores()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/
DThumb2InstrInfo.cpp220 MIB.addReg(DestReg, RegState::ImplicitDefine); in loadRegFromStackSlot()
DARMExpandPseudoInsts.cpp569 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead)); in ExpandVLD()
735 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead)); in ExpandLaneOp()
1597 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead)); in ExpandMI()

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