/external/llvm/lib/Target/AMDGPU/ |
D | SIFrameLowering.cpp | 249 .addReg(ScratchRsrcReg, RegState::ImplicitDefine); in emitPrologue() 253 .addReg(ScratchRsrcReg, RegState::ImplicitDefine); in emitPrologue() 257 .addReg(ScratchRsrcReg, RegState::ImplicitDefine); in emitPrologue() 261 .addReg(ScratchRsrcReg, RegState::ImplicitDefine); in emitPrologue()
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D | SIRegisterInfo.cpp | 601 .addReg(MI->getOperand(0).getReg(), RegState::ImplicitDefine); in eliminateFrameIndex() 624 .addReg(MI->getOperand(0).getReg(), RegState::ImplicitDefine); in eliminateFrameIndex()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
D | SIFrameLowering.cpp | 389 .addReg(ScratchRsrcReg, RegState::ImplicitDefine); in emitEntryFunctionScratchSetup() 411 .addReg(ScratchRsrcReg, RegState::ImplicitDefine); in emitEntryFunctionScratchSetup() 430 .addReg(ScratchRsrcReg, RegState::ImplicitDefine) in emitEntryFunctionScratchSetup() 453 .addReg(ScratchRsrcReg, RegState::ImplicitDefine); in emitEntryFunctionScratchSetup() 471 .addReg(ScratchRsrcReg, RegState::ImplicitDefine); in emitEntryFunctionScratchSetup() 479 .addReg(ScratchRsrcReg, RegState::ImplicitDefine); in emitEntryFunctionScratchSetup() 483 .addReg(ScratchRsrcReg, RegState::ImplicitDefine); in emitEntryFunctionScratchSetup() 489 .addReg(ScratchRsrcReg, RegState::ImplicitDefine); in emitEntryFunctionScratchSetup() 493 .addReg(ScratchRsrcReg, RegState::ImplicitDefine); in emitEntryFunctionScratchSetup()
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D | SIRegisterInfo.cpp | 904 MIB.addReg(SuperReg, RegState::ImplicitDefine); in restoreSGPR() 918 MIB.addReg(SuperReg, RegState::ImplicitDefine); in restoreSGPR() 947 MIB.addReg(MI->getOperand(0).getReg(), RegState::ImplicitDefine); in restoreSGPR()
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D | SILowerControlFlow.cpp | 198 .addReg(AMDGPU::EXEC, RegState::ImplicitDefine); in emitIf()
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/external/llvm/lib/Target/SystemZ/ |
D | SystemZElimCompare.cpp | 217 .addReg(SystemZ::CC, RegState::ImplicitDefine | RegState::Dead); in convertToBRCT() 231 .addReg(SystemZ::CC, RegState::ImplicitDefine); in convertToLoadAndTest() 449 .addReg(SystemZ::CC, RegState::ImplicitDefine | RegState::Dead); in fuseCompareOperations()
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D | SystemZShortenInst.cpp | 147 .addReg(SystemZ::CC, RegState::ImplicitDefine | RegState::Dead); in shortenOn001AddCC()
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D | SystemZFrameLowering.cpp | 269 MIB.addReg(Reg, RegState::ImplicitDefine); in restoreCalleeSavedRegisters()
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/external/swiftshader/third_party/LLVM/lib/Target/Blackfin/ |
D | BlackfinRegisterInfo.cpp | 146 .addReg(Reg, RegState::ImplicitDefine); in loadConstant() 151 .addReg(Reg, RegState::ImplicitDefine); in loadConstant()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/SystemZ/ |
D | SystemZElimCompare.cpp | 239 MIB.addReg(SystemZ::CC, RegState::ImplicitDefine | RegState::Dead); in convertToBRCT() 575 RegState::ImplicitDefine | RegState::Dead); in fuseCompareOperations()
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D | SystemZShortenInst.cpp | 147 .addReg(SystemZ::CC, RegState::ImplicitDefine | RegState::Dead); in shortenOn001AddCC()
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D | SystemZFrameLowering.cpp | 277 MIB.addReg(Reg, RegState::ImplicitDefine); in restoreCalleeSavedRegisters()
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/external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
D | MachineInstrBuilder.h | 37 ImplicitDefine = Implicit | Define, enumerator
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/external/swiftshader/third_party/LLVM/lib/Target/SystemZ/ |
D | SystemZFrameLowering.cpp | 346 MIB.addReg(Reg, RegState::ImplicitDefine); in restoreCalleeSavedRegisters()
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/external/llvm/include/llvm/CodeGen/ |
D | MachineInstrBuilder.h | 42 ImplicitDefine = Implicit | Define, enumerator
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/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/ |
D | MachineInstrBuilder.h | 55 ImplicitDefine = Implicit | Define, enumerator
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/external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
D | ARMExpandPseudoInsts.cpp | 461 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead)); in ExpandVLD() 600 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead)); in ExpandLaneOp() 997 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead)); in ExpandMI()
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/external/llvm/lib/Target/Mips/ |
D | MipsFastISel.cpp | 707 Mips::FCC0, RegState::ImplicitDefine); in emitCmp() 1884 .addReg(Mips::HI0, RegState::ImplicitDefine | RegState::Dead) in fastEmitInst_rr() 1885 .addReg(Mips::LO0, RegState::ImplicitDefine | RegState::Dead); in fastEmitInst_rr()
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D | MipsSEISelDAGToDAG.cpp | 51 IsDef ? RegState::ImplicitDefine : RegState::Implicit | RegState::Undef; in addDSPCtrlRegOperands()
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/external/llvm/lib/Target/ARM/ |
D | ARMExpandPseudoInsts.cpp | 446 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead)); in ExpandVLD() 590 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead)); in ExpandLaneOp() 1403 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead)); in ExpandMI()
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D | Thumb2InstrInfo.cpp | 205 MIB.addReg(DestReg, RegState::ImplicitDefine); in loadRegFromStackSlot()
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D | ARMBaseInstrInfo.cpp | 1096 MIB.addReg(DestReg, RegState::ImplicitDefine); in loadRegFromStackSlot() 1129 MIB.addReg(DestReg, RegState::ImplicitDefine); in loadRegFromStackSlot() 1150 MIB.addReg(DestReg, RegState::ImplicitDefine); in loadRegFromStackSlot() 1170 MIB.addReg(DestReg, RegState::ImplicitDefine); in loadRegFromStackSlot()
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D | ARMFrameLowering.cpp | 1256 .addReg(SupReg, RegState::ImplicitDefine)); in emitAlignedDPRCS2Restores() 1271 .addReg(SupReg, RegState::ImplicitDefine)); in emitAlignedDPRCS2Restores()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
D | Thumb2InstrInfo.cpp | 220 MIB.addReg(DestReg, RegState::ImplicitDefine); in loadRegFromStackSlot()
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D | ARMExpandPseudoInsts.cpp | 569 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead)); in ExpandVLD() 735 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead)); in ExpandLaneOp() 1597 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead)); in ExpandMI()
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