| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMInstrNEON.td | 1831 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1834 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm))))]>;
1838 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1841 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm))))]>;
1856 ValueType TyD, ValueType TyQ, Intrinsic IntOp>
1859 [(set DPR:$Vd, (TyD (IntOp (TyQ QPR:$Vm))))]>;
1874 ValueType TyQ, ValueType TyD, Intrinsic IntOp>
1877 [(set QPR:$Vd, (TyQ (IntOp (TyD DPR:$Vm))))]>;
1980 ValueType ResTy, ValueType OpTy, Intrinsic IntOp, bit Commutable>
1984 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]> {
[all …]
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMInstrNEON.td | 2450 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2453 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm))))]>;
2457 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2460 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm))))]>;
2465 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2468 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm))))]>;
2472 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2475 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm))))]>;
2480 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2483 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm))))]>;
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | ARMInstrNEON.td | 2541 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2544 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm))))]>;
2548 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2551 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm))))]>;
2556 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2559 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm))))]>;
2563 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2566 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm))))]>;
2571 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2574 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm))))]>;
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/WebAssembly/AsmParser/ |
| D | WebAssemblyAsmParser.cpp | 78 struct IntOp { struct
93 struct IntOp Int;
102 WebAssemblyOperand(KindTy K, SMLoc Start, SMLoc End, IntOp I) in WebAssemblyOperand()
307 Int.getEndLoc(), WebAssemblyOperand::IntOp{Val})); in ParseSingleInteger()
342 RParen.getEndLoc(), WebAssemblyOperand::IntOp{0})); in ParseOperandStartingWithInteger()
444 NameLoc, WebAssemblyOperand::IntOp{-1})); in ParseInstruction()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/NVPTX/ |
| D | NVPTXIntrinsics.td | 107 multiclass SHFL<NVPTXRegClass regclass, string mode, Intrinsic IntOp> {
116 [(set regclass:$dst, (IntOp regclass:$src, Int32Regs:$offset, Int32Regs:$mask))]>;
122 [(set regclass:$dst, (IntOp regclass:$src, imm:$offset, Int32Regs:$mask))]>;
128 [(set regclass:$dst, (IntOp regclass:$src, Int32Regs:$offset, imm:$mask))]>;
134 [(set regclass:$dst, (IntOp regclass:$src, imm:$offset, imm:$mask))]>;
146 multiclass SHFL_SYNC<NVPTXRegClass regclass, string mode, Intrinsic IntOp> {
155 [(set regclass:$dst, (IntOp Int32Regs:$threadmask, regclass:$src,
162 [(set regclass:$dst, (IntOp Int32Regs:$threadmask, regclass:$src,
169 [(set regclass:$dst, (IntOp Int32Regs:$threadmask, regclass:$src,
176 [(set regclass:$dst, (IntOp Int32Regs:$threadmask, regclass:$src,
[all …]
|
| /external/llvm/lib/Target/NVPTX/ |
| D | NVPTXIntrinsics.td | 69 multiclass SHFL<NVPTXRegClass regclass, string mode, Intrinsic IntOp> {
78 [(set regclass:$dst, (IntOp regclass:$src, Int32Regs:$offset, Int32Regs:$mask))]>;
84 [(set regclass:$dst, (IntOp regclass:$src, imm:$offset, Int32Regs:$mask))]>;
90 [(set regclass:$dst, (IntOp regclass:$src, Int32Regs:$offset, imm:$mask))]>;
96 [(set regclass:$dst, (IntOp regclass:$src, imm:$offset, imm:$mask))]>;
882 string SpaceStr, string TypeStr, string OpcStr, PatFrag IntOp,
890 [(set regclass:$dst, (IntOp ptrclass:$addr, regclass:$b))]>,
898 [(set regclass:$dst, (IntOp ptrclass:$addr, IMM:$b))]>,
902 string OpcStr, PatFrag IntOp, Operand IMMType, SDNode IMM, Predicate Pred> {
904 IntOp, IMMType, IMM, Pred>;
[all …]
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64InstrFormats.td | 5233 Intrinsic IntOp> {
5237 [(set (v8i8 V64:$Rd), (IntOp (v8i16 V128:$Rn), (v8i16 V128:$Rm)))]>;
5245 [(set (v4i16 V64:$Rd), (IntOp (v4i32 V128:$Rn), (v4i32 V128:$Rm)))]>;
5253 [(set (v2i32 V64:$Rd), (IntOp (v2i64 V128:$Rn), (v2i64 V128:$Rm)))]>;
5262 def : Pat<(concat_vectors (v8i8 V64:$Rd), (IntOp (v8i16 V128:$Rn),
5267 def : Pat<(concat_vectors (v4i16 V64:$Rd), (IntOp (v4i32 V128:$Rn),
5272 def : Pat<(concat_vectors (v2i32 V64:$Rd), (IntOp (v2i64 V128:$Rn),
5280 Intrinsic IntOp> {
5284 [(set (v8i16 V128:$Rd), (IntOp (v8i8 V64:$Rn), (v8i8 V64:$Rm)))]>;
5297 def : Pat<(v8i16 (IntOp (v8i8 (extract_high_v16i8 V128:$Rn)),
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| D | AArch64InstrFormats.td | 5685 Intrinsic IntOp> {
5689 [(set (v8i8 V64:$Rd), (IntOp (v8i16 V128:$Rn), (v8i16 V128:$Rm)))]>;
5697 [(set (v4i16 V64:$Rd), (IntOp (v4i32 V128:$Rn), (v4i32 V128:$Rm)))]>;
5705 [(set (v2i32 V64:$Rd), (IntOp (v2i64 V128:$Rn), (v2i64 V128:$Rm)))]>;
5714 def : Pat<(concat_vectors (v8i8 V64:$Rd), (IntOp (v8i16 V128:$Rn),
5719 def : Pat<(concat_vectors (v4i16 V64:$Rd), (IntOp (v4i32 V128:$Rn),
5724 def : Pat<(concat_vectors (v2i32 V64:$Rd), (IntOp (v2i64 V128:$Rn),
5732 Intrinsic IntOp> {
5736 [(set (v8i16 V128:$Rd), (IntOp (v8i8 V64:$Rn), (v8i8 V64:$Rm)))]>;
5749 def : Pat<(v8i16 (IntOp (v8i8 (extract_high_v16i8 V128:$Rn)),
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 37051 SDValue IntOp = DAG.getNode(IntOpcode, dl, IntVT, Op0, Op1); in lowerX86FPLogicOp() local
37052 return DAG.getBitcast(VT, IntOp); in lowerX86FPLogicOp()
|