| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 639 bit IsLoad = ?;
782 let IsLoad = 1;
786 let IsLoad = 1;
792 let IsLoad = 1;
796 let IsLoad = 1;
800 let IsLoad = 1;
805 let IsLoad = 1;
809 let IsLoad = 1;
813 let IsLoad = 1;
817 let IsLoad = 1;
[all …]
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCVSXSwapRemoval.cpp | 78 unsigned int IsLoad : 1; member
343 SwapVector[VecIdx].IsLoad = 1; in gatherVectorInstructions()
349 SwapVector[VecIdx].IsLoad = 1; in gatherVectorInstructions()
358 SwapVector[VecIdx].IsLoad = 1; in gatherVectorInstructions()
663 else if (SwapVector[EntryIdx].IsLoad && SwapVector[EntryIdx].IsSwap) { in recordUnoptimizableWebs()
674 if (!SwapVector[UseIdx].IsSwap || SwapVector[UseIdx].IsLoad || in recordUnoptimizableWebs()
698 if (!SwapVector[DefIdx].IsSwap || SwapVector[DefIdx].IsLoad || in recordUnoptimizableWebs()
748 if (SwapVector[EntryIdx].IsLoad && SwapVector[EntryIdx].IsSwap) { in markSwapsForRemoval()
967 if (SwapVector[EntryIdx].IsLoad) in dumpSwapVector()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/ |
| D | PPCVSXSwapRemoval.cpp | 79 unsigned int IsLoad : 1; member
346 SwapVector[VecIdx].IsLoad = 1; in gatherVectorInstructions()
352 SwapVector[VecIdx].IsLoad = 1; in gatherVectorInstructions()
363 SwapVector[VecIdx].IsLoad = 1; in gatherVectorInstructions()
672 else if (SwapVector[EntryIdx].IsLoad && SwapVector[EntryIdx].IsSwap) { in recordUnoptimizableWebs()
683 if (!SwapVector[UseIdx].IsSwap || SwapVector[UseIdx].IsLoad || in recordUnoptimizableWebs()
707 if (!SwapVector[DefIdx].IsSwap || SwapVector[DefIdx].IsLoad || in recordUnoptimizableWebs()
758 if (SwapVector[EntryIdx].IsLoad && SwapVector[EntryIdx].IsSwap) { in markSwapsForRemoval()
984 if (SwapVector[EntryIdx].IsLoad) in dumpSwapVector()
|
| /external/llvm/lib/Target/NVPTX/ |
| D | NVPTXInstrFormats.td | 36 bit IsLoad = 0;
52 let TSFlags{5-5} = IsLoad;
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/NVPTX/ |
| D | NVPTXInstrFormats.td | 36 bit IsLoad = 0;
52 let TSFlags{5-5} = IsLoad;
|
| /external/llvm/lib/CodeGen/ |
| D | AtomicExpandPass.cpp | 51 bool IsStore, bool IsLoad);
227 bool IsStore, IsLoad; in runOnFunction() local
232 IsLoad = true; in runOnFunction()
237 IsLoad = false; in runOnFunction()
242 IsStore = IsLoad = true; in runOnFunction()
253 IsStore = IsLoad = true; in runOnFunction()
257 MadeChange |= bracketInstWithFences(I, FenceOrdering, IsStore, IsLoad); in runOnFunction()
324 bool IsStore, bool IsLoad) { in bracketInstWithFences() argument
327 auto LeadingFence = TLI->emitLeadingFence(Builder, Order, IsStore, IsLoad); in bracketInstWithFences()
329 auto TrailingFence = TLI->emitTrailingFence(Builder, Order, IsStore, IsLoad); in bracketInstWithFences()
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| /external/swiftshader/third_party/subzero/src/ |
| D | IceAssemblerARM32.cpp | 934 bool IsLoad, bool IsByte, IValueT Rt, in emitMemOp() argument
939 (InstType << kTypeShift) | (IsLoad ? L : 0) | in emitMemOp()
944 void AssemblerARM32::emitMemOp(CondARM32::Cond Cond, bool IsLoad, bool IsByte, in emitMemOp() argument
972 emitMemOp(Cond, kInstTypeMemImmediate, IsLoad, IsByte, Rt, Address); in emitMemOp()
995 emitMemOp(Cond, kInstTypeRegisterShift, IsLoad, IsByte, Rt, Address); in emitMemOp()
1143 BlockAddressMode AddressMode, bool IsLoad, in emitMultiMemOp() argument
1149 AddressMode | (IsLoad ? L : 0) | (BaseReg << kRnShift) | in emitMultiMemOp()
1549 constexpr bool IsLoad = true; in ldr() local
1580 emitMemOp(Cond, IsLoad, IsByte, Rt, OpAddress, TInfo, LdrName); in ldr()
1612 emitMemOp(Cond, IsLoad, IsByte, Rt, OpAddress, TInfo, LdrName); in ldr()
[all …]
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| D | IceAssemblerARM32.h | 745 void emitMemOp(CondARM32::Cond Cond, IValueT InstType, bool IsLoad,
754 void emitMemOp(CondARM32::Cond Cond, bool IsLoad, bool IsByte, IValueT Rt,
765 void emitMemExOp(CondARM32::Cond, Type Ty, bool IsLoad, const Operand *OpRd,
773 bool IsLoad, IValueT BaseReg, IValueT Registers);
|
| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/Analysis/ |
| D | Loads.h | 127 bool *IsLoad, unsigned *NumScanedInst);
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Analysis/ |
| D | Loads.cpp | 325 AliasAnalysis *AA, bool *IsLoad, in FindAvailableLoadedValue() argument
333 ScanFrom, MaxInstsToScan, AA, IsLoad, NumScanedInst); in FindAvailableLoadedValue()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/utils/TableGen/ |
| D | X86FoldTablesEmitter.cpp | 100 bool IsLoad = false; member in __anon67ff85150111::X86FoldTablesEmitter::X86FoldTableEntry
114 if (E.IsLoad) in operator <<()
460 Result.IsLoad = true; in addEntryWithFlags()
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| /external/clang/lib/StaticAnalyzer/Core/ |
| D | CheckerManager.cpp | 293 bool IsLoad; member
305 : Checkers(checkers), Loc(loc), IsLoad(isLoad), NodeEx(NodeEx), in CheckLocationContext()
310 ProgramPoint::Kind K = IsLoad ? ProgramPoint::PreLoadKind : in runChecker()
317 checkFn(Loc, IsLoad, BoundEx, C); in runChecker()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/Utils/ |
| D | X86ShuffleDecode.h | 146 void DecodeScalarMoveMask(unsigned NumElts, bool IsLoad,
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| D | X86ShuffleDecode.cpp | 406 void DecodeScalarMoveMask(unsigned NumElts, bool IsLoad, in DecodeScalarMoveMask() argument
412 Mask.push_back(IsLoad ? static_cast<int>(SM_SentinelZero) : i); in DecodeScalarMoveMask()
|
| /external/llvm/lib/Target/X86/Utils/ |
| D | X86ShuffleDecode.h | 129 void DecodeScalarMoveMask(MVT VT, bool IsLoad,
|
| /external/clang/lib/StaticAnalyzer/Checkers/ |
| D | CheckerDocumentation.cpp | 137 void checkLocation(SVal Loc, bool IsLoad, const Stmt *S, in checkLocation() argument
|
| /external/deqp-deps/SPIRV-Tools/source/opt/ |
| D | instruction.h | 324 inline bool IsLoad() const;
719 bool Instruction::IsLoad() const { return spvOpcodeIsLoad(opcode()); } in IsLoad() function
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| D | value_number_table.cpp | 75 if (inst->IsLoad() && !inst->IsReadOnlyLoad()) { in AssignValueNumber()
|
| /external/swiftshader/third_party/SPIRV-Tools/source/opt/ |
| D | instruction.h | 324 inline bool IsLoad() const;
719 bool Instruction::IsLoad() const { return spvOpcodeIsLoad(opcode()); } in IsLoad() function
|
| D | value_number_table.cpp | 75 if (inst->IsLoad() && !inst->IsReadOnlyLoad()) { in AssignValueNumber()
|
| /external/v8/src/compiler/ |
| D | node-matchers.h | 768 if (l.IsLoad() && r.IsLoadStackPointer()) { in MatchedInternal()
770 if (mleft.object().IsLoad() && mleft.index().Is(0) && in MatchedInternal()
797 if (l.IsLoad() && r.IsLoadStackPointer()) { in MatchedInternal()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | ARMLoadStoreOptimizer.cpp | 495 bool IsLoad = in UpdateBaseRegUses() local
500 if (IsLoad || IsStore) { in UpdateBaseRegUses()
826 bool IsLoad = isi32Load(Opcode); in CreateLoadStoreDouble() local
827 assert((IsLoad || isi32Store(Opcode)) && "Must have integer load or store"); in CreateLoadStoreDouble()
828 unsigned LoadStoreOpcode = IsLoad ? ARM::t2LDRDi8 : ARM::t2STRDi8; in CreateLoadStoreDouble()
833 if (IsLoad) { in CreateLoadStoreDouble()
848 bool IsLoad = isLoadSingle(Opcode); in MergeOpsUpdate() local
863 if (IsLoad) { in MergeOpsUpdate()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMLoadStoreOptimizer.cpp | 470 bool IsLoad = in UpdateBaseRegUses() local
475 if (IsLoad || IsStore) { in UpdateBaseRegUses()
795 bool IsLoad = isi32Load(Opcode); in CreateLoadStoreDouble() local
796 assert((IsLoad || isi32Store(Opcode)) && "Must have integer load or store"); in CreateLoadStoreDouble()
797 unsigned LoadStoreOpcode = IsLoad ? ARM::t2LDRDi8 : ARM::t2STRDi8; in CreateLoadStoreDouble()
802 if (IsLoad) { in CreateLoadStoreDouble()
817 bool IsLoad = isLoadSingle(Opcode); in MergeOpsUpdate() local
832 if (IsLoad) { in MergeOpsUpdate()
|
| /external/capstone/arch/AArch64/ |
| D | AArch64Disassembler.c | 1004 bool IsLoad; in DecodeSignedLdStInstruction() local
1178 IsLoad = fieldFromInstruction(insn, 22, 1) != 0; in DecodeSignedLdStInstruction()
1183 if (IsLoad && IsIndexed && !IsFP && Rn != 31 && Rt == Rn) in DecodeSignedLdStInstruction()
1273 bool IsLoad = fieldFromInstruction(insn, 22, 1) != 0; in DecodePairLdStInstruction() local
1383 if (IsLoad && Rt == Rt2) in DecodePairLdStInstruction()
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| /external/clang/lib/CodeGen/ |
| D | CGAtomic.cpp | 1023 bool IsLoad = E->getOp() == AtomicExpr::AO__c11_atomic_load || in EmitAtomicExpr() local
1045 if (IsLoad) in EmitAtomicExpr()
1051 if (IsLoad || IsStore) in EmitAtomicExpr()
1078 if (!IsLoad) in EmitAtomicExpr()
1080 if (!IsLoad && !IsStore) in EmitAtomicExpr()
1107 if (!IsLoad) { in EmitAtomicExpr()
1115 if (!IsLoad && !IsStore) { in EmitAtomicExpr()
|