Searched refs:IsSP (Results 1 – 13 of 13) sorted by relevance
308 VIXL_ASSERT(!reg.IsSP()); in Operand()319 VIXL_ASSERT(!reg.IsSP()); in Operand()406 VIXL_ASSERT(!regoffset.IsSP()); in MemOperand()426 VIXL_ASSERT(regoffset.Is64Bits() && !regoffset.IsSP()); in MemOperand()453 VIXL_ASSERT(regoffset_.Is64Bits() && !regoffset_.IsSP()); in MemOperand()467 VIXL_ASSERT(!regoffset_.IsSP()); in MemOperand()
467 temp = rd.IsSP() ? temps.AcquireSameSizeAs(rd) : rd; in MoveImmediateHelper()498 if (rd.IsSP()) { in MoveImmediateHelper()514 if (IsImmMovz(imm, reg_size) && !dst.IsSP()) { in OneInstrMoveImmediateHelper()521 } else if (IsImmMovn(imm, reg_size) && !dst.IsSP()) { in OneInstrMoveImmediateHelper()880 PreShiftImmMode mode = rn.IsSP() ? kNoShift : kAnyShift; in LogicalMacro()1220 VIXL_ASSERT(!rd.IsZero() && !rd.IsSP()); in CselHelper()1221 VIXL_ASSERT(left.IsImmediate() || !left.GetRegister().IsSP()); in CselHelper()1222 VIXL_ASSERT(right.IsImmediate() || !right.GetRegister().IsSP()); in CselHelper()1752 if (rd.IsSP()) { in AddSubMacro()1756 } else if (rn.IsSP()) { in AddSubMacro()
183 bool IsSP() const { in IsSP() function
2419 if (rd.IsSP() || rm.IsSP()) { in mov()5100 if (rn.IsSP() || rd.IsSP()) { in AddSub()5101 VIXL_ASSERT(!(rd.IsSP() && (S == SetFlags))); in AddSub()
280 static bool IsSP(const MachineOperand &MO) { in INITIALIZE_PASS()442 if (!IsSP(MI->getOperand(1))) in ReduceXWtoXWSP()511 if (!isMMThreeBitGPRegister(MI->getOperand(0)) || !IsSP(MI->getOperand(1))) in ReduceADDIUToADDIUR1SP()529 if (!IsSP(MI->getOperand(0)) || !IsSP(MI->getOperand(1))) in ReduceADDIUToADDIUSP()
49 inline bool CPURegister::IsSP() const { in IsSP() function279 DCHECK_IMPLIES(reg.IsSP(), shift_amount == 0);291 DCHECK(!reg.IsSP());428 DCHECK(!regoffset.IsSP());443 DCHECK(regoffset.Is64Bits() && !regoffset.IsSP());464 DCHECK(regoffset_.Is64Bits() && !regoffset_.IsSP());478 DCHECK(!regoffset_.IsSP());
192 if (rd.IsSP()) { in LogicalMacro()266 Register temp = rd.IsSP() ? temps.AcquireSameSizeAs(rd) : rd; in Mov()292 if (rd.IsSP()) { in Mov()306 Register dst = (rd.IsSP()) ? temps.AcquireSameSizeAs(rd) : rd; in Mov()358 DCHECK(rd.IsSP()); in Mov()644 if (IsImmMovz(imm, reg_size) && !dst.IsSP()) { in TryOneInstrMoveImmediate()649 } else if (IsImmMovn(imm, reg_size) && !dst.IsSP()) { in TryOneInstrMoveImmediate()
389 DCHECK(!rd.IsSP() && rd.Is64Bits()); in CzeroX()400 DCHECK(!rd.IsSP()); in CmovX()
2258 if (rd.IsSP() || rm.IsSP()) { in mov()4032 if (rn.IsSP() || rd.IsSP()) { in AddSub()4033 DCHECK(!(rd.IsSP() && (S == SetFlags))); in AddSub()
166 bool IsSP() const;
18234 !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) { in vld1()18265 !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) { in vld1()18279 (nreglist.GetLength() == 1) && !rm.IsPC() && !rm.IsSP() && in vld1()18295 !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) { in vld1()18325 !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) { in vld1()18338 (nreglist.GetLength() == 1) && !rm.IsPC() && !rm.IsSP() && in vld1()18614 !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) { in vld2()18639 !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) { in vld2()18655 !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) { in vld2()18672 !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) { in vld2()[all …]
146 bool IsSP() const { return GetCode() == kSpCode; } in IsSP() function
1073 ((operand.GetImmediate() & 0x3) == 0) && rd.IsLow() && rn.IsSP()) || in Add()1079 !operand.GetBaseRegister().IsSP() && in Add()1082 (operand.IsPlainRegister() && !rd.IsPC() && rn.IsSP() && in Add()2083 operand.GetBaseRegister().IsSP() && in Ldr()4415 operand.GetBaseRegister().IsSP() && in Str()