| /external/libxaac/decoder/armv7/ |
| D | ixheaacd_mps_synt_pre_twiddle.s | 32 LOOP1: label
53 BGT LOOP1
|
| D | ixheaacd_conv_ergtoamplitudelp.s | 34 LOOP1: label
135 BGT LOOP1
142 BGT LOOP1
|
| D | ixheaacd_mps_synt_post_twiddle.s | 32 LOOP1: label
53 BGT LOOP1
|
| D | ixheaacd_mps_synt_post_fft_twiddle.s | 37 LOOP1: label
63 BGT LOOP1
|
| D | ixheaacd_mps_synt_out_calc.s | 21 LOOP1: label
49 BGT LOOP1
|
| D | ixheaacd_fwd_modulation.s | 38 LOOP1: label
52 BPL LOOP1
|
| D | ixheaacd_calc_pre_twid.s | 36 LOOP1: label
77 BGT LOOP1
|
| D | ixheaacd_calc_post_twid.s | 37 LOOP1: label
79 BGT LOOP1
|
| D | ixheaacd_harm_idx_zerotwolp.s | 41 LOOP1: label
76 BGT LOOP1
|
| D | ixheaacd_esbr_fwd_modulation.s | 36 LOOP1: label
61 BGT LOOP1
|
| D | ixheaacd_conv_ergtoamplitude.s | 34 LOOP1: label
126 BGT LOOP1
|
| D | ixheaacd_tns_parcor2lpc_32x16.s | 35 LOOP1: label
39 BGT LOOP1
|
| D | ixheaacd_esbr_cos_sin_mod_loop2.s | 94 LOOP1: label
152 BGT LOOP1
|
| D | ixheaacd_rescale_subbandsamples.s | 54 LOOP1: label
73 BGT LOOP1
|
| D | ixheaacd_esbr_cos_sin_mod_loop1.s | 37 LOOP1: label
144 BGT LOOP1
|
| D | ixheaacd_apply_rot.s | 31 LOOP1: label
71 BGT LOOP1
|
| D | ia_xheaacd_mps_reoder_mulshift_acc.s | 58 LOOP1: label
95 BGT LOOP1
|
| D | ixheaacd_cos_sin_mod.s | 89 LOOP1: label
217 BGT LOOP1
|
| /external/llvm/test/CodeGen/X86/ |
| D | twoaddr-coalesce-3.ll | 22 ; CHECK: [[LOOP1:^[a-zA-Z0-9_.]+]]: {{#.*}} %for.body
28 ; CHECK: jl [[LOOP1]]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/X86/ |
| D | twoaddr-coalesce-3.ll | 22 ; CHECK: [[LOOP1:^[a-zA-Z0-9_.]+]]: {{#.*}} %for.body{{$}}
28 ; CHECK: jl [[LOOP1]]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/ |
| D | infinite-loop.ll | 78 ; SI: [[LOOP1:BB[0-9]+_[0-9]+]]: ; %loop1
81 ; SI: s_cbranch_vccnz [[LOOP1]]
|
| D | indirect-addressing-si.ll | 343 ; GCN: [[LOOP1:BB[0-9]+_[0-9]+]]:
356 ; GCN: s_cbranch_execnz [[LOOP1]]
414 ; GCN: [[LOOP1:BB[0-9]+_[0-9]+]]:
427 ; GCN: s_cbranch_execnz [[LOOP1]]
|
| /external/libxaac/decoder/armv8/ |
| D | ixheaacd_cos_sin_mod_loop2.s | 131 LOOP1: label
208 BGT LOOP1
|
| D | ixheaacd_cos_sin_mod_loop1.s | 50 LOOP1: label
200 BGT LOOP1
|
| /external/llvm/test/CodeGen/AMDGPU/ |
| D | indirect-addressing-si.ll | 225 ; CHECK: [[LOOP1:BB[0-9]+_[0-9]+]]:
232 ; CHECK: s_cbranch_execnz [[LOOP1]]
282 ; CHECK: [[LOOP1:BB[0-9]+_[0-9]+]]:
289 ; CHECK: s_cbranch_execnz [[LOOP1]]
|