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Searched refs:LoRegList (Results 1 – 3 of 3) sorted by relevance

/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMCallingConv.h76 static const unsigned LoRegList[] = { ARM::R1, ARM::R3 }; in f64AssignAAPCS() local
97 unsigned T = State.AllocateReg(LoRegList[i]); in f64AssignAAPCS()
99 assert(T == LoRegList[i] && "Could not allocate register"); in f64AssignAAPCS()
102 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, LoRegList[i], in f64AssignAAPCS()
122 static const unsigned LoRegList[] = { ARM::R1, ARM::R3 }; in f64RetAssign() local
124 unsigned Reg = State.AllocateReg(HiRegList, LoRegList, 2); in f64RetAssign()
134 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, LoRegList[i], in f64RetAssign()
/external/llvm/lib/Target/ARM/
DARMCallingConv.h75 static const MCPhysReg LoRegList[] = { ARM::R1, ARM::R3 }; in f64AssignAAPCS() local
102 unsigned T = State.AllocateReg(LoRegList[i]); in f64AssignAAPCS()
104 assert(T == LoRegList[i] && "Could not allocate register"); in f64AssignAAPCS()
107 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, LoRegList[i], in f64AssignAAPCS()
127 static const MCPhysReg LoRegList[] = { ARM::R1, ARM::R3 }; in f64RetAssign() local
129 unsigned Reg = State.AllocateReg(HiRegList, LoRegList); in f64RetAssign()
139 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, LoRegList[i], in f64RetAssign()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/
DARMCallingConv.h75 static const MCPhysReg LoRegList[] = { ARM::R1, ARM::R3 }; in f64AssignAAPCS() local
102 unsigned T = State.AllocateReg(LoRegList[i]); in f64AssignAAPCS()
104 assert(T == LoRegList[i] && "Could not allocate register"); in f64AssignAAPCS()
107 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, LoRegList[i], in f64AssignAAPCS()
127 static const MCPhysReg LoRegList[] = { ARM::R1, ARM::R3 }; in f64RetAssign() local
129 unsigned Reg = State.AllocateReg(HiRegList, LoRegList); in f64RetAssign()
139 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, LoRegList[i], in f64RetAssign()