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Searched refs:MASK (Results 1 – 25 of 201) sorted by relevance

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/external/swiftshader/third_party/SPIRV-Tools/test/
Dtext_to_binary.image_test.cpp52 #define MASK(NAME) SpvImageOperands##NAME##Mask macro
61 {" Bias %5", {MASK(Bias), 5}},
62 {" Lod %5", {MASK(Lod), 5}},
63 {" Grad %5 %6", {MASK(Grad), 5, 6}},
64 {" ConstOffset %5", {MASK(ConstOffset), 5}},
65 {" Offset %5", {MASK(Offset), 5}},
66 {" ConstOffsets %5", {MASK(ConstOffsets), 5}},
67 {" Sample %5", {MASK(Sample), 5}},
68 {" MinLod %5", {MASK(MinLod), 5}},
70 #undef MASK
[all …]
/external/deqp-deps/SPIRV-Tools/test/
Dtext_to_binary.image_test.cpp52 #define MASK(NAME) SpvImageOperands##NAME##Mask macro
61 {" Bias %5", {MASK(Bias), 5}},
62 {" Lod %5", {MASK(Lod), 5}},
63 {" Grad %5 %6", {MASK(Grad), 5, 6}},
64 {" ConstOffset %5", {MASK(ConstOffset), 5}},
65 {" Offset %5", {MASK(Offset), 5}},
66 {" ConstOffsets %5", {MASK(ConstOffsets), 5}},
67 {" Sample %5", {MASK(Sample), 5}},
68 {" MinLod %5", {MASK(MinLod), 5}},
70 #undef MASK
[all …]
/external/libvpx/libvpx/third_party/libyuv/source/
Drow_any.cc34 #define ANY41C(NAMEANY, ANY_SIMD, UVSHIFT, DUVSHIFT, BPP, MASK) \ argument
40 int r = width & MASK; \
41 int n = width & ~MASK; \
50 yuvconstants, MASK + 1); \
70 #define ANY31(NAMEANY, ANY_SIMD, UVSHIFT, DUVSHIFT, BPP, MASK) \ argument
75 int r = width & MASK; \
76 int n = width & ~MASK; \
83 ANY_SIMD(temp, temp + 64, temp + 128, temp + 192, MASK + 1); \
126 #define ANY31C(NAMEANY, ANY_SIMD, UVSHIFT, DUVSHIFT, BPP, MASK) \ argument
132 int r = width & MASK; \
[all …]
Dscale_any.cc22 #define CANY(NAMEANY, TERP_SIMD, TERP_C, BPP, MASK) \ argument
25 int r = dst_width & MASK; \
26 int n = dst_width & ~MASK; \
63 #define SDANY(NAMEANY, SCALEROWDOWN_SIMD, SCALEROWDOWN_C, FACTOR, BPP, MASK) \ argument
66 int r = (int)((unsigned int)dst_width % (MASK + 1)); /* NOLINT */ \
78 #define SDODD(NAMEANY, SCALEROWDOWN_SIMD, SCALEROWDOWN_C, FACTOR, BPP, MASK) \ argument
81 int r = (int)((unsigned int)(dst_width - 1) % (MASK + 1)); /* NOLINT */ \
388 #define SDAANY(NAMEANY, SCALEROWDOWN_SIMD, SCALEROWDOWN_C, BPP, MASK) \ argument
391 int r = dst_width & MASK; \
392 int n = dst_width & ~MASK; \
[all …]
Drotate_any.cc21 #define TANY(NAMEANY, TPOS_SIMD, MASK) \ argument
24 int r = width & MASK; \
46 #define TUVANY(NAMEANY, TPOS_SIMD, MASK) \ argument
50 int r = width & MASK; \
/external/libyuv/files/source/
Drow_any.cc34 #define ANY41C(NAMEANY, ANY_SIMD, UVSHIFT, DUVSHIFT, BPP, MASK) \ argument
40 int r = width & MASK; \
41 int n = width & ~MASK; \
50 yuvconstants, MASK + 1); \
70 #define ANY31(NAMEANY, ANY_SIMD, UVSHIFT, DUVSHIFT, BPP, MASK) \ argument
75 int r = width & MASK; \
76 int n = width & ~MASK; \
83 ANY_SIMD(temp, temp + 64, temp + 128, temp + 192, MASK + 1); \
114 #define ANY31C(NAMEANY, ANY_SIMD, UVSHIFT, DUVSHIFT, BPP, MASK) \ argument
120 int r = width & MASK; \
[all …]
Dscale_any.cc22 #define CANY(NAMEANY, TERP_SIMD, TERP_C, BPP, MASK) \ argument
25 int n = dst_width & ~MASK; \
29 TERP_C(dst_ptr + n * BPP, src_ptr, dst_width & MASK, x + n * dx, dx); \
48 #define SDANY(NAMEANY, SCALEROWDOWN_SIMD, SCALEROWDOWN_C, FACTOR, BPP, MASK) \ argument
51 int r = (int)((unsigned int)dst_width % (MASK + 1)); \
63 #define SDODD(NAMEANY, SCALEROWDOWN_SIMD, SCALEROWDOWN_C, FACTOR, BPP, MASK) \ argument
66 int r = (int)((unsigned int)(dst_width - 1) % (MASK + 1)); \
353 #define SDAANY(NAMEANY, SCALEROWDOWN_SIMD, SCALEROWDOWN_C, BPP, MASK) \ argument
356 int r = (int)((unsigned int)dst_width % (MASK + 1)); \
403 #define SAANY(NAMEANY, SCALEADDROW_SIMD, SCALEADDROW_C, MASK) \ argument
[all …]
/external/llvm/test/CodeGen/AArch64/
Darm64-neon-select_cc.ll8 ; CHECK: cmeq [[MASK:v[0-9]+]].8b, v[[LHS]].8b, v[[RHS]].8b
9 ; CHECK: dup [[DUPMASK:v[0-9]+]].8b, [[MASK]].b[0]
18 ; CHECK: fcmeq [[MASK:v[0-9]+]].2s, v0.2s, v1.2s
19 ; CHECK-NEXT: dup [[DUPMASK:v[0-9]+]].2s, [[MASK]].s[0]
28 ; CHECK: fcmeq d[[MASK:[0-9]+]], d0, d1
29 ; CHECK-NEXT: bsl v[[MASK]].8b, v2.8b, v3.8b
39 ; CHECK: cmeq [[MASK:v[0-9]+]].16b, v[[LHS]].16b, v[[RHS]].16b
40 ; CHECK: dup [[DUPMASK:v[0-9]+]].16b, [[MASK]].b[0]
49 ; CHECK: fcmeq [[MASK:v[0-9]+]].4s, v0.4s, v1.4s
50 ; CHECK-NEXT: dup [[DUPMASK:v[0-9]+]].4s, [[MASK]].s[0]
[all …]
Dfast-isel-cmp-vec.ll14 ; CHECK-NEXT: movi.2s [[MASK:v[0-9]+]], #1
15 ; CHECK-NEXT: and.8b v0, [[CMP]], [[MASK]]
29 ; CHECK-NEXT: movi.2s [[MASK:v[0-9]+]], #1
30 ; CHECK-NEXT: and.8b v0, v[[CMP]], [[MASK]]
45 ; CHECK-NEXT: movi.4h [[MASK:v[0-9]+]], #1
46 ; CHECK-NEXT: and.8b [[ZEXT:v[0-9]+]], [[CMPV4I16]], [[MASK]]
61 ; CHECK-NEXT: movi.4h [[MASK:v[0-9]+]], #1
62 ; CHECK-NEXT: and.8b [[ZEXT:v[0-9]+]], v[[CMP]], [[MASK]]
77 ; CHECK-NEXT: movi.16b [[MASK:v[0-9]+]], #1
78 ; CHECK-NEXT: and.16b v0, [[CMP]], [[MASK]]
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/
Darm64-neon-select_cc.ll8 ; CHECK: cmeq [[MASK:v[0-9]+]].8b, v[[LHS]].8b, v[[RHS]].8b
9 ; CHECK: dup [[DUPMASK:v[0-9]+]].8b, [[MASK]].b[0]
18 ; CHECK: fcmeq [[MASK:v[0-9]+]].2s, v0.2s, v1.2s
19 ; CHECK-NEXT: dup [[DUPMASK:v[0-9]+]].2s, [[MASK]].s[0]
28 ; CHECK: fcmeq d[[MASK:[0-9]+]], d0, d1
29 ; CHECK-NEXT: bsl v[[MASK]].8b, v2.8b, v3.8b
39 ; CHECK: cmeq [[MASK:v[0-9]+]].16b, v[[LHS]].16b, v[[RHS]].16b
40 ; CHECK: dup [[DUPMASK:v[0-9]+]].16b, [[MASK]].b[0]
49 ; CHECK: fcmeq [[MASK:v[0-9]+]].4s, v0.4s, v1.4s
50 ; CHECK-NEXT: dup [[DUPMASK:v[0-9]+]].4s, [[MASK]].s[0]
[all …]
Dfast-isel-cmp-vec.ll14 ; CHECK-NEXT: movi.2s [[MASK:v[0-9]+]], #1
15 ; CHECK-NEXT: and.8b v0, [[CMP]], [[MASK]]
29 ; CHECK-NEXT: movi.2s [[MASK:v[0-9]+]], #1
30 ; CHECK-NEXT: and.8b v0, v[[CMP]], [[MASK]]
45 ; CHECK-NEXT: movi.4h [[MASK:v[0-9]+]], #1
46 ; CHECK-NEXT: and.8b [[ZEXT:v[0-9]+]], [[CMPV4I16]], [[MASK]]
61 ; CHECK-NEXT: movi.4h [[MASK:v[0-9]+]], #1
62 ; CHECK-NEXT: and.8b [[ZEXT:v[0-9]+]], v[[CMP]], [[MASK]]
77 ; CHECK-NEXT: movi.16b [[MASK:v[0-9]+]], #1
78 ; CHECK-NEXT: and.16b v0, [[CMP]], [[MASK]]
[all …]
/external/llvm/test/Transforms/InstCombine/
Dicmp-logical.ll5 ; CHECK: [[MASK:%.*]] = and i32 %A, 7
6 ; CHECK: icmp ne i32 [[MASK]], 0
22 ; CHECK: [[MASK:%.*]] = and i32 %A, 7
23 ; CHECK: icmp eq i32 [[MASK]], 0
39 ; CHECK: [[MASK:%.*]] = and i32 %A, 7
40 ; CHECK: icmp ne i32 [[MASK]], 7
56 ; CHECK: [[MASK:%.*]] = and i32 %A, 7
57 ; CHECK: icmp eq i32 [[MASK]], 7
73 ; CHECK: [[MASK:%.*]] = and i32 %A, 39
74 ; CHECK: icmp ne i32 [[MASK]], %A
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/CodeGenPrepare/X86/
Dx86-shuffle-sink.ll12 ; CHECK-NEXT: [[MASK:%.*]] = shufflevector <16 x i8> [[TMP:%.*]], <16 x i8> undef, <16 x i32> ze…
15 ; CHECK-NEXT: ret <16 x i8> [[MASK]]
17 ; CHECK-NEXT: [[RES:%.*]] = shl <16 x i8> [[LHS:%.*]], [[MASK]]
33 ; CHECK-SSE2-NEXT: [[MASK:%.*]] = shufflevector <8 x i16> [[TMP:%.*]], <8 x i16> undef, <8 x i32…
36 ; CHECK-SSE2-NEXT: ret <8 x i16> [[MASK]]
43 ; CHECK-XOP-NEXT: [[MASK:%.*]] = shufflevector <8 x i16> [[TMP:%.*]], <8 x i16> undef, <8 x i32>…
46 ; CHECK-XOP-NEXT: ret <8 x i16> [[MASK]]
48 ; CHECK-XOP-NEXT: [[RES:%.*]] = shl <8 x i16> [[LHS:%.*]], [[MASK]]
52 ; CHECK-AVX2-NEXT: [[MASK:%.*]] = shufflevector <8 x i16> [[TMP:%.*]], <8 x i16> undef, <8 x i32…
55 ; CHECK-AVX2-NEXT: ret <8 x i16> [[MASK]]
[all …]
/external/libaom/libaom/third_party/libyuv/source/
Drow_any.cc26 #define ANY31(NAMEANY, ANY_SIMD, UVSHIFT, DUVSHIFT, BPP, MASK) \ argument
31 int r = width & MASK; \
32 int n = width & ~MASK; \
39 ANY_SIMD(temp, temp + 64, temp + 128, temp + 192, MASK + 1); \
122 #define ANY21(NAMEANY, ANY_SIMD, UVSHIFT, SBPP, SBPP2, BPP, MASK) \ argument
127 int r = width & MASK; \
128 int n = width & ~MASK; \
135 ANY_SIMD(temp, temp + 64, temp + 128, MASK + 1); \
225 #define ANY11(NAMEANY, ANY_SIMD, UVSHIFT, SBPP, BPP, MASK) \ argument
229 int r = width & MASK; \
[all …]
Dscale_any.cc22 #define CANY(NAMEANY, TERP_SIMD, TERP_C, BPP, MASK) \ argument
25 int n = dst_width & ~MASK; \
30 dst_width & MASK, x + n * dx, dx); \
46 #define SDANY(NAMEANY, SCALEROWDOWN_SIMD, SCALEROWDOWN_C, FACTOR, BPP, MASK) \ argument
49 int r = (int)((unsigned int)dst_width % (MASK + 1)); \
146 #define SDAANY(NAMEANY, SCALEROWDOWN_SIMD, SCALEROWDOWN_C, BPP, MASK) \ argument
149 int r = (int)((unsigned int)dst_width % (MASK + 1)); \
172 #define SAANY(NAMEANY, SCALEADDROW_SIMD, SCALEADDROW_C, MASK) \ argument
174 int n = src_width & ~MASK; \
178 SCALEADDROW_C(src_ptr + n, dst_ptr + n, src_width & MASK); \
/external/jemalloc_new/include/jemalloc/internal/
Dextent_structs.h89 #define MASK(CURRENT_FIELD_WIDTH, CURRENT_FIELD_SHIFT) ((((((uint64_t)0x1U) << (CURRENT_FIELD_WIDTH… macro
93 #define EXTENT_BITS_ARENA_MASK MASK(EXTENT_BITS_ARENA_WIDTH, EXTENT_BITS_ARENA_SHIFT)
97 #define EXTENT_BITS_SLAB_MASK MASK(EXTENT_BITS_SLAB_WIDTH, EXTENT_BITS_SLAB_SHIFT)
101 #define EXTENT_BITS_COMMITTED_MASK MASK(EXTENT_BITS_COMMITTED_WIDTH, EXTENT_BITS_COMMITTED_SHIFT)
105 #define EXTENT_BITS_DUMPABLE_MASK MASK(EXTENT_BITS_DUMPABLE_WIDTH, EXTENT_BITS_DUMPABLE_SHIFT)
109 #define EXTENT_BITS_ZEROED_MASK MASK(EXTENT_BITS_ZEROED_WIDTH, EXTENT_BITS_ZEROED_SHIFT)
113 #define EXTENT_BITS_STATE_MASK MASK(EXTENT_BITS_STATE_WIDTH, EXTENT_BITS_STATE_SHIFT)
117 #define EXTENT_BITS_SZIND_MASK MASK(EXTENT_BITS_SZIND_WIDTH, EXTENT_BITS_SZIND_SHIFT)
121 #define EXTENT_BITS_NFREE_MASK MASK(EXTENT_BITS_NFREE_WIDTH, EXTENT_BITS_NFREE_SHIFT)
/external/lua/src/
Dlctype.h46 #define MASK(B) (1 << (B)) macro
57 #define lislalpha(c) testprop(c, MASK(ALPHABIT))
58 #define lislalnum(c) testprop(c, (MASK(ALPHABIT) | MASK(DIGITBIT)))
59 #define lisdigit(c) testprop(c, MASK(DIGITBIT))
60 #define lisspace(c) testprop(c, MASK(SPACEBIT))
61 #define lisprint(c) testprop(c, MASK(PRINTBIT))
62 #define lisxdigit(c) testprop(c, MASK(XDIGITBIT))
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/
Dpermute.ll4 ; GCN: v_mov_b32_e32 [[MASK:v[0-9]+]], 0x6050400
5 ; GCN: v_perm_b32 v{{[0-9]+}}, {{[vs][0-9]+}}, {{[vs][0-9]+}}, [[MASK]]
19 ; GCN: v_mov_b32_e32 [[MASK:v[0-9]+]], 0x7060503
20 ; GCN: v_perm_b32 v{{[0-9]+}}, {{[vs][0-9]+}}, {{[vs][0-9]+}}, [[MASK]]
34 ; GCN: v_mov_b32_e32 [[MASK:v[0-9]+]], 0x7060503
35 ; GCN: v_perm_b32 v{{[0-9]+}}, {{[vs][0-9]+}}, {{[vs][0-9]+}}, [[MASK]]
50 ; GCN: v_mov_b32_e32 [[MASK:v[0-9]+]], 0x7020500
51 ; GCN: v_perm_b32 v{{[0-9]+}}, {{[vs][0-9]+}}, {{[vs][0-9]+}}, [[MASK]]
65 ; GCN: v_mov_b32_e32 [[MASK:v[0-9]+]], 0x6050403
66 ; GCN: v_perm_b32 v{{[0-9]+}}, {{[vs][0-9]+}}, {{[vs][0-9]+}}, [[MASK]]
[all …]
/external/u-boot/board/micronas/vct/
Dgpio.c22 #define MASK(pin) (1 << ((pin) & 0x1F)) macro
46 clrsetbits(GPIO_SWPORTA_DDR(gpio_base), MASK(pin), 0); in vct_gpio_dir()
48 clrsetbits(GPIO_SWPORTA_DDR(gpio_base), 0, MASK(pin)); in vct_gpio_dir()
60 clrsetbits(GPIO_SWPORTA_DR(gpio_base), MASK(pin), 0); in vct_gpio_set()
62 clrsetbits(GPIO_SWPORTA_DR(gpio_base), 0, MASK(pin)); in vct_gpio_set()
73 return ((value & MASK(pin)) ? 1 : 0); in vct_gpio_get()
/external/arm-optimized-routines/math/single/
Dieee_status.c17 # define MASK (1<<27)|FE_IEEE_FLUSHZERO|FE_IEEE_MASK_ALL_EXCEPT|FE_IEEE_ALL_EXCEPT|FE_IEEE_ROUND_MA… in __ieee_status() macro
19 # define MASK (1<<27)|FE_IEEE_FLUSHZERO|FE_IEEE_MASK_ALL_EXCEPT|FE_IEEE_ALL_EXCEPT in __ieee_status() macro
23 bicmask &= MASK; in __ieee_status()
24 xormask &= MASK; in __ieee_status()
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/NVPTX/
Dmatch.ll8 ; CHECK: ld.param.u32 [[MASK:%r[0-9]+]], [match.any.sync.i32_param_0];
11 ; CHECK: match.any.sync.b32 [[V0:%r[0-9]+]], [[VALUE]], [[MASK]];
15 ; CHECK: match.any.sync.b32 [[V2:%r[0-9]+]], 2, [[MASK]];
27 ; CHECK: ld.param.u32 [[MASK:%r[0-9]+]], [match.any.sync.i64_param_0];
30 ; CHECK: match.any.sync.b64 [[V0:%rd[0-9]+]], [[VALUE]], [[MASK]];
34 ; CHECK: match.any.sync.b64 [[V2:%rd[0-9]+]], 2, [[MASK]];
49 ; CHECK: ld.param.u32 [[MASK:%r[0-9]+]], [match.all.sync.i32p_param_0];
52 ; CHECK: match.all.sync.b32 {{%r[0-9]+\|%p[0-9]+}}, [[VALUE]], [[MASK]];
57 ; CHECK: match.all.sync.b32 {{%r[0-9]+\|%p[0-9]+}}, 1, [[MASK]];
85 ; CHECK: ld.param.u32 [[MASK:%r[0-9]+]], [match.all.sync.i64p_param_0];
[all …]
/external/linux-kselftest/tools/testing/selftests/bpf/
Dtest_pkt_md_access.c16 #define TEST_FIELD(TYPE, FIELD, MASK) \ argument
19 if (tmp != ((*(volatile __u32 *)&skb->FIELD) & MASK)) \
24 #define TEST_FIELD(TYPE, FIELD, MASK) \ argument
28 if (tmp != ((*(volatile __u32 *)&skb->FIELD) & MASK)) \
/external/lzma/C/
DPpmd7Enc.c77 #define MASK(sym) ((signed char *)charMask)[sym] macro
112 MASK(s->Symbol) = 0; in Ppmd7_EncodeSymbol()
114 do { MASK((--s)->Symbol) = 0; } while (--i); in Ppmd7_EncodeSymbol()
135 MASK(s->Symbol) = 0; in Ppmd7_EncodeSymbol()
168 sum += (s->Freq & (int)(MASK(s->Symbol))); in Ppmd7_EncodeSymbol()
178 sum += (s->Freq & (int)(MASK(cur))); in Ppmd7_EncodeSymbol()
179 MASK(cur) = 0; in Ppmd7_EncodeSymbol()
/external/llvm/test/CodeGen/X86/
Dvec_uint_to_fp.ll43 ; SSE: movdqa [[MASKCSTADDR]](%rip), [[MASK:%xmm[0-9]+]]
44 ; SSE-NEXT: pand %xmm0, [[MASK]]
45 ; After this instruction, MASK will have the value of the low parts
47 ; SSE-NEXT: por [[LOWCSTADDR]](%rip), [[MASK]]
51 ; SSE-NEXT: addps [[MASK]], %xmm0
102 ; SSE: movdqa {{.*#+}} [[MASK:xmm[0-9]+]] = [65535,65535,65535,65535]
104 ; SSE-NEXT: pand %[[MASK]], [[VECLOW]]
113 ; MASK is the low vector of the second part after this point.
114 ; SSE-NEXT: pand %xmm1, %[[MASK]]
115 ; SSE-NEXT: por %[[LOWCST]], %[[MASK]]
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/X86/
Dvec_uint_to_fp.ll43 ; SSE: movdqa [[MASKCSTADDR]](%rip), [[MASK:%xmm[0-9]+]]
44 ; SSE-NEXT: pand %xmm0, [[MASK]]
45 ; After this instruction, MASK will have the value of the low parts
47 ; SSE-NEXT: por [[LOWCSTADDR]](%rip), [[MASK]]
51 ; SSE-NEXT: addps [[MASK]], %xmm0
102 ; SSE: movdqa {{.*#+}} [[MASK:xmm[0-9]+]] = [65535,65535,65535,65535]
104 ; SSE-NEXT: pand %[[MASK]], [[VECLOW]]
113 ; MASK is the low vector of the second part after this point.
114 ; SSE-NEXT: pand %xmm1, %[[MASK]]
115 ; SSE-NEXT: por %[[LOWCST]], %[[MASK]]
[all …]

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