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Searched refs:MCTL_LPDDR3_MR2 (Results 1 – 2 of 2) sorted by relevance

/external/u-boot/arch/arm/include/asm/arch-sunxi/
Ddram_sun8i_a83t.h202 #define MCTL_LPDDR3_MR2 0xa /* RL=12, CWL=6 */ macro
/external/u-boot/arch/arm/mach-sunxi/
Ddram_sun8i_a83t.c141 writel(MCTL_LPDDR3_MR2, &mctl_ctl->mr2); in auto_set_timing_para()