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Searched refs:MCTL_MR0 (Results 1 – 6 of 6) sorted by relevance

/external/u-boot/arch/arm/include/asm/arch-sunxi/
Ddram_sun8i_a33.h173 #define MCTL_MR0 0x1c70 /* CL=11, WR=12 */ macro
Ddram_sun8i_a83t.h195 #define MCTL_MR0 0x1c70 /* CL=11, WR=12 */ macro
Ddram_sun6i.h347 #define MCTL_MR0 0x1a50 macro
/external/u-boot/arch/arm/mach-sunxi/
Ddram_sun8i_a33.c133 writel(MCTL_MR0, &mctl_ctl->mr0); in auto_set_timing_para()
Ddram_sun8i_a83t.c134 writel(MCTL_MR0, &mctl_ctl->mr0); in auto_set_timing_para()
Ddram_sun6i.c122 writel(MCTL_MR0, &mctl_phy->mr0); in mctl_channel_init()